JPS59161847A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59161847A JPS59161847A JP3580983A JP3580983A JPS59161847A JP S59161847 A JPS59161847 A JP S59161847A JP 3580983 A JP3580983 A JP 3580983A JP 3580983 A JP3580983 A JP 3580983A JP S59161847 A JPS59161847 A JP S59161847A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- board
- ceramic substrate
- multilayer ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000007789 sealing Methods 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 description 17
- 239000000758 substrate Substances 0.000 description 15
- 239000011295 pitch Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 241000252233 Cyprinus carpio Species 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、複数の半導体デバイスを多層配線基板に搭載
した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device in which a plurality of semiconductor devices are mounted on a multilayer wiring board.
この種の半導体装置に関する従来技術としては、特開昭
５６−７４５７号の「半導体デバイス用パッケージ」が
ある。しかしこれは、セラミック基板の半導体デバイス
搭載面で配線補修用ワイアを布線する方式を採用してい
る為、配線変更が生ずる毎にパッケージを分解し、配線
変更後気密封止とガス封入作業を行なう必要があり、配
線変更が容易でないという欠点がある。As a prior art related to this type of semiconductor device, there is "Package for Semiconductor Device" disclosed in Japanese Patent Application Laid-open No. 7457/1983. However, since this method uses a method of wiring repair wires on the semiconductor device mounting surface of the ceramic substrate, the package must be disassembled each time the wiring is changed, and airtight sealing and gas filling work must be performed after wiring changes. However, there is a drawback that wiring changes are not easy.
本発明の目的は、従来よりも配線変更を容易に行い得る
構造の半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure that allows wiring to be changed more easily than in the past.
本発明のもう１つの目的は、半導体デバイスの交換を容
易化した半導体装置を提供すること番こある。Another object of the present invention is to provide a semiconductor device in which semiconductor devices can be easily replaced.
本発明の別の目的は、多層配線基板の入出力ピンのピッ
チと異なるピッチのスルーホールを有スる外部のプリン
ト基板をこ実装できる半導体装置を提供することにある
。Another object of the present invention is to provide a semiconductor device on which an external printed circuit board having through holes having a pitch different from that of input/output pins of a multilayer wiring board can be mounted.
本発明は上記目的を達成するために、多層配線基板の下
面（半導体デバイス搭載面と反対の面）に補修布線用パ
ッドを設けるとともに、多層配線基板の下面に設けた人
出力ビンを直接外部へ引き出すのではなく、それと着脱
可能に結合するコネクタボードを介して外部へ引き出し
、さら番こ、半導体デバイスの搭載空間を気密封止する
ためのキャップを多層配線基板の上面にロウ付けするこ
とを特徴とするものである。In order to achieve the above object, the present invention provides a repair wiring pad on the bottom surface of a multilayer wiring board (the surface opposite to the surface on which semiconductor devices are mounted), and connects the human output bin provided on the bottom surface of the multilayer wiring board directly to the outside. Rather than pulling it out to the outside through a connector board that is removably connected to it, a cap is soldered to the top of the multilayer wiring board to hermetically seal the mounting space for the semiconductor device. This is a characteristic feature.
以下、本発明の一実施例（こついて第１図ないし第４図
により説明する。Hereinafter, one embodiment of the present invention will be explained with reference to FIGS. 1 to 4.
第１図は本発明に係る半導体装置の分解斜視図であり、
１は多層セラミック基板（多層配線基板）であり、その
上面に半導体デバイス２が搭載される。多層セラミック
基板１の上面の周縁部には封止用メタライズパターン３
が形成され、ここ（こコバール製の封止用キャップ６が
８０Ａｕ−８ｎロウ材でロウ接するようになっている。FIG. 1 is an exploded perspective view of a semiconductor device according to the present invention,
1 is a multilayer ceramic substrate (multilayer wiring board), and a semiconductor device 2 is mounted on the upper surface thereof. A metallized pattern 3 for sealing is provided at the periphery of the upper surface of the multilayer ceramic substrate 1.
is formed, and a sealing cap 6 made of Kovar is brazed thereto with 80Au-8N brazing material.
多層セラミック基板１の下面には、入出力ピン５とガイ
ドピン４が設けられ、さらに図示しない補修布線用パッ
ドが設けられている。An input/output pin 5 and a guide pin 4 are provided on the lower surface of the multilayer ceramic substrate 1, and a repair wiring pad (not shown) is also provided.
７はコネクタボードであり、その上面側には人出力ビン
５と着脱可能に結合するコンタクト８と、ガイドビン４
と係合するガイドボスト１０が設けられている。コネク
タボード７の下面には、外部のプリント基板（第２図）
のスルーホールに半田付けされる外部ピン９が設けられ
ている。この外部ピン９とコンタクト８は配列ピッチが
図示のように一致していなくともよく（勿論、一致させ
ることもできる）、それぞれの対応するもの同士はコネ
クタボード７上において電気的に接続されている。Reference numeral 7 designates a connector board, and on its upper surface side there are contacts 8 that are removably connected to the human output bin 5, and guide bins 4.
A guide post 10 is provided which engages with. An external printed circuit board (Fig. 2) is attached to the bottom of the connector board 7.
An external pin 9 is provided which is soldered to the through-hole of. The arrangement pitches of the external pins 9 and the contacts 8 do not have to match as shown in the figure (of course, they can also match), and the corresponding ones are electrically connected to each other on the connector board 7. .
１１はクランパであり、多層セラミック基板１とコネク
タボード７とを結合状態にクランプするために用いられ
る。A clamper 11 is used to clamp the multilayer ceramic substrate 1 and the connector board 7 together.
第２図は半導体装置を外部のプリント基板に実装した状
態を示す断面図である。この図によって、半導体装置の
組立てと実装の方法について説明する。FIG. 2 is a sectional view showing a semiconductor device mounted on an external printed circuit board. A method for assembling and mounting a semiconductor device will be explained with reference to this diagram.
先ず、セラミック基板１に半導体デバイス２をフリップ
チップ方式で搭載する。次に、Ｎ２またはＨｅガス雰囲
気中において、封止用キャップ６を８０Ａｕ−８ｎロウ
材２０を用いて多層セラミック基板１のメタライズパタ
ーン３にロウ接し、気密封止する。次に、予めプリント
基板１３のスルーホールに半田付けしておいたコネクタ
ボード７のコンタクト８に、多層セラミック基板１の入
出力ビン５を結合させる。この際の位置合せは、ガイド
ビン４とガイドボスト１０の係合によってなされる。そ
して、クランパ１１を取り付け、多層セラミック基板１
とコネクタボード７とを結合状態をニクランブする。First, the semiconductor device 2 is mounted on the ceramic substrate 1 using a flip-chip method. Next, in an N2 or He gas atmosphere, the sealing cap 6 is soldered to the metallized pattern 3 of the multilayer ceramic substrate 1 using an 80Au-8N brazing material 20, and hermetically sealed. Next, the input/output pins 5 of the multilayer ceramic board 1 are coupled to the contacts 8 of the connector board 7, which have been soldered to the through holes of the printed circuit board 13 in advance. The alignment at this time is achieved by engagement between the guide bin 4 and the guide post 10. Then, the clamper 11 is attached, and the multilayer ceramic substrate 1 is
and the connector board 7 are connected to each other.
なお、このようにクランプした状態で、コネクタボード
７の外部ピン９をプリント基板１３昏こ半田付けするこ
とも可能である。Note that it is also possible to solder the external pins 9 of the connector board 7 to the printed circuit board 13 in this clamped state.
第３図は多層セラミック基板１の一部を拡大して示す断
ｍ１図であり、１４は格子変換層、１５は電源層、１６
は信号層である。多層セラミック基板１の上面（こは、
フリップチップタイプの半導体デバイス２の半田電極２
１が接続されるパッド２２が設けられており、このパッ
ド２２は必要な内部配線を行うためにスルーホールパタ
ーン２３で格子変換層１４へ適適引き出され、更にスル
ーホールパターン２４を介して下面の補修布線用パット
１７に引き出された後、下面の配線パターン１８および
スルーホールパターン２５を介して信号層１６へ導かれ
、必要な相互結線がなされる。この相互結線の一部は、
スルーホールパターン２６を通じて入出力ピン５に引き
出される。１２は補修布線用の被覆線である。FIG. 3 is an enlarged cross-sectional view of a part of the multilayer ceramic substrate 1, in which 14 is a lattice conversion layer, 15 is a power supply layer, and 16
is the signal layer. The upper surface of the multilayer ceramic substrate 1 (
Solder electrode 2 of flip chip type semiconductor device 2
A pad 22 to which 1 is connected is provided, and this pad 22 is suitably drawn out to the lattice conversion layer 14 through a through-hole pattern 23 in order to perform necessary internal wiring, and is further connected to the lower surface through the through-hole pattern 24. After being drawn out to the repair wiring pad 17, it is guided to the signal layer 16 via the wiring pattern 18 and through-hole pattern 25 on the lower surface, and necessary mutual connections are made. Some of this interconnection is
It is led out to the input/output pin 5 through the through hole pattern 26. 12 is a covered wire for repair wiring.
第４図は配線変更の説明図である。即ち、補修布線用パ
ッド１７ａ、１７ｂのそれまでの接結を断ち、新た（こ
相互に接結するような配線変更が必要となった場合、パ
ッド１７ａと配線パターン１８ａ１パツド１７ｂと配線
パターン１８ｂをレーザ等によって途中で切断する。つ
いで、被覆線１２（例えば、金メッキ線番こポリイミド
樹脂を被覆しＴこワイヤ）をパッド１７ａ、１７ｂＧこ
ボンディングし、相互に接続する。FIG. 4 is an explanatory diagram of wiring changes. That is, if it becomes necessary to change the wiring such that the repair wiring pads 17a and 17b are connected to each other, the connection between the pads 17a and 17b and the wiring pattern 18b is changed. The pads 17a and 17b are then bonded to the covered wires 12 (for example, gold-plated wires coated with polyimide resin) and connected to each other.
本実施例の半導体装置は、次のような利点がある。The semiconductor device of this embodiment has the following advantages.
（１）クランプ１１を取り外して多層セラミック基板１
をコイ・フタボード７がら引き抜き、多層セラミック基
板１の下面を露出させれば、補修布線用バッド１７を利
用して配線変更を行うことができる。このように、配線
変更作業のために封止用キャップ６を取り外したり、再
封止を行う必要がない。(1) Remove the clamp 11 and remove the multilayer ceramic substrate 1.
By pulling it out from the carp/lid board 7 and exposing the bottom surface of the multilayer ceramic substrate 1, wiring can be changed using the repair wiring pad 17. In this way, there is no need to remove the sealing cap 6 or perform resealing for wiring change work.
（１１）封止キャップ６は多層セラミック基板１の上面
をこ低融点ロウ材でロウ接しであるので、取外し一再封
止が簡単であり、半導体デバイス２の交換が容易である
。(11) Since the sealing cap 6 is soldered to the upper surface of the multilayer ceramic substrate 1 using a low melting point brazing material, it is easy to remove and reseal, and the semiconductor device 2 is easy to replace.
（１１０人出力ビン５をコネクタボード７を介して外部
へ引き出すため、コネクタボード７上にて入出力ピン５
と外部ビン９のピッチ変換を簡単に行うことができる。(In order to pull out the 110 person output bin 5 to the outside via the connector board 7, connect the input/output pin 5 on the connector board 7.
The pitch of the external bin 9 can be easily changed.
したがって、多層セラミック基板１側を変更することな
く、任意のスルーホールピッチを持つプリント基板１３
に半導体装置を実装できる。Therefore, without changing the multilayer ceramic substrate 1 side, the printed circuit board 13 can have any through hole pitch.
Semiconductor devices can be mounted on.
以上の説明から明らかなように、本発明によれば、配線
変更や半導体デバイスの交換が容易で、かつ多層配線基
板を変更すること′なく任意のスルーホールピッチを持
つプリント基板に実装可能な半導体装置を実現できるも
のであり、その効果は顕著である。As is clear from the above description, according to the present invention, it is possible to easily change wiring and replace semiconductor devices, and to mount a semiconductor on a printed circuit board having an arbitrary through-hole pitch without changing the multilayer wiring board. The device can be realized, and its effects are remarkable.
第１図は本発明の一実施例を示す分解斜視図、第２図は
同実施例のプリント基板に実装した状態を示す断面図、
第３図は多層セラミック基板の一部を拡大して示す断面
図、第４図は配線変更の説明図である。
１・・・多層セラミック基板、 ２・・・半導体デバ
イス、 ５・・・入出力ビン、 ６・・・封止用キ
ャップ、７・・・コネクタボード、 ８・・・コンタ
クト、９・・・外部ピン。
第３図
１ｆ７４ 図FIG. 1 is an exploded perspective view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing the same embodiment mounted on a printed circuit board.
FIG. 3 is an enlarged sectional view of a part of the multilayer ceramic substrate, and FIG. 4 is an explanatory diagram of wiring changes. DESCRIPTION OF SYMBOLS 1... Multilayer ceramic board, 2... Semiconductor device, 5... Input/output bin, 6... Sealing cap, 7... Connector board, 8... Contact, 9... External pin. Figure 3 1f74
Claims (1)
数の半導体デバイスと、該多層配線基板の上面にロウ接
された封止用キャップと、該多層配線基板の下面に設け
られた入出力ビンおよび補修布線用パッドと、該入出力
ビンの対応するものと着脱可能に結合するコンタクトを
上面に有し、該コンタクトの対応するものと電気的に接
続された外部ビンを下面に有するコネクタボードとを具
備することを特徴とする半導体装置。A multilayer wiring board, a plurality of semiconductor devices mounted on the top surface of the multilayer wiring board, a sealing cap soldered to the top surface of the multilayer wiring board, and input/output devices provided on the bottom surface of the multilayer wiring board. A connector having a pin and repair wiring pad, a contact detachably coupled to a corresponding one of the input/output bin on the upper surface, and an external pin electrically connected to the corresponding one of the contacts on the lower surface. A semiconductor device comprising: a board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3580983A JPS59161847A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3580983A JPS59161847A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161847A true JPS59161847A (en) | 1984-09-12 |
Family
ID=12452251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3580983A Pending JPS59161847A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161847A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0645484A (en) * | 1992-07-23 | 1994-02-18 | Melco:Kk | Integrated circuit element and conversion connector mountable therewith |
| WO2002019427A2 (en) * | 2000-08-30 | 2002-03-07 | Advanced Micro Devices, Inc. | Integrated circuit package incorporating camouflaged programmable elements |
-
1983
- 1983-03-07 JP JP3580983A patent/JPS59161847A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0645484A (en) * | 1992-07-23 | 1994-02-18 | Melco:Kk | Integrated circuit element and conversion connector mountable therewith |
| WO2002019427A2 (en) * | 2000-08-30 | 2002-03-07 | Advanced Micro Devices, Inc. | Integrated circuit package incorporating camouflaged programmable elements |
| WO2002019427A3 (en) * | 2000-08-30 | 2002-08-15 | Advanced Micro Devices Inc | Integrated circuit package incorporating camouflaged programmable elements |
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