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JPH04267361A - Leadless chip carrier - Google Patents

Leadless chip carrier

Info

Publication number
JPH04267361A
JPH04267361A JP3028481A JP2848191A JPH04267361A JP H04267361 A JPH04267361 A JP H04267361A JP 3028481 A JP3028481 A JP 3028481A JP 2848191 A JP2848191 A JP 2848191A JP H04267361 A JPH04267361 A JP H04267361A
Authority
JP
Japan
Prior art keywords
insulating substrate
lcc
element mounting
mounting part
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3028481A
Other languages
Japanese (ja)
Inventor
Shigemi Nakamura
中村 茂美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3028481A priority Critical patent/JPH04267361A/en
Publication of JPH04267361A publication Critical patent/JPH04267361A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To constitute a miniature memory module by connecting the external terminals on the opposite sides of an LCC(leadless chip carrier) thereby stacking a plurality of LCCs. CONSTITUTION:An element mounting part is provided in the center of an insulating substrate 4 having inner terminals 5 arranged around the element mounting part and an insulating substrate 3 having bored part corresponding to the element mounting part is then press bonded to the insulating substrate 4 and integrated therewith. An IC chip 1 is then mounted on the element mounting part of an LCC substrate having an external terminal 9 connected with an inner terminal on the side face and pads 7, 8 arranged on the upper and lower faces of the insulating substrates 3, 4 and connected with the external terminal 9. Electrode of the IC chip 1 and the inner terminal are then bonded with a thin metal wire 2 and only the bored part is sealed with sealing resin 6 thus constituting the LCC. Since the sealing resin 6 does not extend over the top face of the insulating substrate 3, the pads 7, 8 of the external terminal 9 are formed on the opposite faces of the LCC and utilized for interconnection.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はリードレスチップキャリ
ア(以下LCCと記す)に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless chip carrier (hereinafter referred to as LCC).

【0002】0002

【従来の技術】従来のLCCは、図3に示すように、中
央部に素子搭載用の凹部を設けた絶縁基板14にICチ
ップ1を搭載し、金属細線2により絶縁基板14に設け
た内部端子5に接続し、絶縁基板14の上に封止樹脂の
流れ防止の為に、樹脂枠15を設けたLCC基板の素子
搭載部にICチップ1を搭載し、封止樹脂6で封止する
。また、LCC基板の側面には外部端子9を設けて内部
端子5と接続し、LCCを構成する。
[Prior Art] As shown in FIG. 3, in a conventional LCC, an IC chip 1 is mounted on an insulating substrate 14 having a recessed part for mounting an element in the center, and an inner part of the insulating substrate 14 is provided with thin metal wires 2. The IC chip 1 is connected to the terminal 5, mounted on the element mounting part of the LCC substrate provided with a resin frame 15 to prevent the sealing resin from flowing onto the insulating substrate 14, and sealed with the sealing resin 6. . Furthermore, external terminals 9 are provided on the side surface of the LCC board and connected to internal terminals 5 to form an LCC.

【0003】マザーボードへの実装は、外部端子9に設
けたLCC下面の半田付パッドをマザーボードの搭載ラ
ンドに半田付けして接続される。
[0003] When mounting on a motherboard, a soldering pad on the bottom surface of the LCC provided at the external terminal 9 is soldered to a mounting land on the motherboard.

【0004】なお、LCC上面にもパッドを形成するこ
とは可能であるが、封止樹脂面がパッドより高い位置に
あるため、LCCを重ねて接続することはできない。
[0004]Although it is possible to form a pad on the top surface of the LCC, since the sealing resin surface is located higher than the pad, it is not possible to connect the LCCs in an overlapping manner.

【0005】図4はメモリICを複数個使用するメモリ
モジュールを一例を示すブロック図である。IC31〜
34は、チップセレクト端子(CS)37〜40を単独
に取り出した以外はアドレスバス36,データバス35
,電源端子を並列接続して回路が構成されている。
FIG. 4 is a block diagram showing an example of a memory module using a plurality of memory ICs. IC31~
34 is an address bus 36 and a data bus 35 except for chip select terminals (CS) 37 to 40 taken out individually.
, the circuit is constructed by connecting the power supply terminals in parallel.

【0006】[0006]

【発明が解決しようとする課題】従来のLCCはマザー
ボードに平面的に実装していたため、実装面積が大きい
という問題点があった。
[Problems to be Solved by the Invention] Conventional LCCs have been mounted flatly on a motherboard, which has led to the problem that the mounting area is large.

【0007】また、マザーボードの両面に搭載すること
も可能であるが、マザーボードの配線が複雑になるとい
う問題点があった。
[0007]Although it is possible to mount the device on both sides of the motherboard, there is a problem in that the wiring on the motherboard becomes complicated.

【0008】[0008]

【課題を解決するための手段】本発明のLCCは、中央
部に素子搭載部を設け前記素子搭載部の周囲に内部端子
を配置して設けた第1の絶縁基板と、前記素子搭載部に
対応する開孔部を有し前記第1の絶縁基板上に設けて一
体化した第2の絶縁基板と、前記内部端子に接続して前
記第1及び第2の絶縁基板の側面に設けた外部端子と、
前記外部端子に接続して前記第1の絶縁基板の下面及び
第2の絶縁基板の上面に設けたパッドと、前記素子搭載
部に搭載して前記内部端子に電気的に接続したICチッ
プと、前記ICチップを含んで前記開口部内のみを封止
した封止樹脂とを有する。
[Means for Solving the Problems] The LCC of the present invention includes a first insulating substrate provided with an element mounting part in the center and internal terminals arranged around the element mounting part; a second insulating substrate having a corresponding opening and integrated with the first insulating substrate; and an external insulating substrate connected to the internal terminal and provided on the side surfaces of the first and second insulating substrates. terminal and
a pad connected to the external terminal and provided on the lower surface of the first insulating substrate and the upper surface of the second insulating substrate; an IC chip mounted on the element mounting portion and electrically connected to the internal terminal; and a sealing resin that includes the IC chip and seals only the inside of the opening.

【0009】[0009]

【実施例】次に本発明について、図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

【0010】図1は本発明の一実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing an embodiment of the present invention.

【0011】図1に示すように、中央部に素子搭載部を
設け、素子搭載部の周囲に内部端子5を設けた絶縁基板
4の上に素子搭載部に対応する開孔部を有する絶縁基板
3を加圧接着して一体化し側面に内部端子と接続した外
部端子9及び外部端子9に接続して絶縁基板3,4の上
面及び下面にパット7,8を設けたLCC基板の素子搭
載部にICチップ1を搭載して金属細線2によりICチ
ップ1の電極と内部端子間をワイヤボンディングし、封
止樹脂6にて開孔部内のみを封止して、LCCを構成す
る。
As shown in FIG. 1, an insulating substrate 4 has an element mounting part in the center and an internal terminal 5 around the element mounting part, and has an opening corresponding to the element mounting part. 3 are integrated by pressure bonding and are connected to internal terminals on the side surfaces, and external terminals 9 are connected to the external terminals 9 and pads 7 and 8 are provided on the upper and lower surfaces of the insulating substrates 3 and 4. The IC chip 1 is mounted on the IC chip 1, wire bonding is performed between the electrodes of the IC chip 1 and the internal terminals using the metal wires 2, and only the inside of the opening is sealed with the sealing resin 6 to form an LCC.

【0012】ここで封止樹脂6が絶縁基板3の上面を越
えない為、外部端子9のパッド7,8をLCCの上下両
面に形成して、接続用に用いることができる。
Since the sealing resin 6 does not exceed the upper surface of the insulating substrate 3, the pads 7 and 8 of the external terminals 9 can be formed on both the upper and lower surfaces of the LCC and used for connection.

【0013】なお、絶縁基板3の厚さを0.8mm、絶
縁基板4の厚さを0.3mmとすると、LCCの総厚は
、最大1.2〜1.3mmに抑えることが可能である。 平面寸法としてはメモリICチップが256Kビットの
スタティックRAMでは10mm×5mm程度である為
、LCCのサイズは、15mm×9mm程度となる。L
CCの端子数は、前記メモリICチップのピン数28に
対して、チップセレクト端子を個別に取出す為、例えば
、4個のメモリモジュールを構成する場合は、3ピン追
加しておくことで、4つのチップセレクト端子を個別に
取り出すことが可能となっている。従って、31ピンの
LCCを4種類用意することにより、容易に超小型のメ
モリモジュールが構成できる。
Note that if the thickness of the insulating substrate 3 is 0.8 mm and the thickness of the insulating substrate 4 is 0.3 mm, the total thickness of the LCC can be suppressed to a maximum of 1.2 to 1.3 mm. . Since the planar dimensions of a 256 Kbit static RAM memory IC chip are approximately 10 mm x 5 mm, the size of the LCC is approximately 15 mm x 9 mm. L
Compared to the 28 pins of the memory IC chip, the number of CC terminals can be reduced to 4 because the chip select terminals are taken out individually.For example, when configuring 4 memory modules, by adding 3 pins, It is possible to take out the two chip select terminals individually. Therefore, by preparing four types of 31-pin LCCs, an ultra-small memory module can be easily constructed.

【0014】図2は本発明のLCCの実装状態を示す模
式的断面図である。
FIG. 2 is a schematic cross-sectional view showing the mounting state of the LCC of the present invention.

【0015】図2に示すように、LCCを複数個積重ね
てパッド7,8間を高温半田10又は導電性接着剤で接
続して設けたモジュールをマザーボード11上に設けた
LCC搭載用ランド12上に搭載し半田13で接合する
As shown in FIG. 2, a module in which a plurality of LCCs are stacked and pads 7 and 8 are connected with high temperature solder 10 or conductive adhesive is mounted on a motherboard 11 on an LCC mounting land 12. Mount it on the board and connect it with solder 13.

【0016】[0016]

【発明の効果】以上説明したように本発明は、LCCの
外部端子を上下両面接続可能とすることにより、複数個
重ねて、非常に小型なメモリモジュールが構成できると
いう効果を有する。
As described above, the present invention has the effect that by making it possible to connect the external terminals of an LCC on both upper and lower sides, a very small memory module can be constructed by stacking a plurality of LCCs.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例の示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】本発明のLCCの実装状態を示す模式的断面図
である。
FIG. 2 is a schematic cross-sectional view showing the mounting state of the LCC of the present invention.

【図3】従来のLCCの一例を示す断面図である。FIG. 3 is a sectional view showing an example of a conventional LCC.

【図4】メモリICを複数個使用するメモリモジュール
の一例を示すブロック図である。
FIG. 4 is a block diagram showing an example of a memory module that uses a plurality of memory ICs.

【符号の説明】[Explanation of symbols]

1    ICチップ 2    金属細線 3,4,14    絶縁基板 5    内部端子 6    封止樹脂 7,8    パッド 9    外部端子 10    高温半田 11    マザーボード 12    LCC搭載ランド 13    半田 15    樹脂枠 31,32,33,34    メモリIC,35  
  データバス 36    アドレスバス
1 IC chip 2 Fine metal wires 3, 4, 14 Insulating substrate 5 Internal terminal 6 Sealing resin 7, 8 Pad 9 External terminal 10 High temperature solder 11 Motherboard 12 LCC mounting land 13 Solder 15 Resin frame 31, 32, 33, 34 Memory IC ,35
Data bus 36 Address bus

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  中央部に素子搭載部を設け前記素子搭
載部の周囲に内部端子を配置して設けた第1の絶縁基板
と、前記素子搭載部に対応する開孔部を有し前記第1の
絶縁基板上に設けて一体化した第2の絶縁基板と、前記
内部端子に接続して前記第1及び第2の絶縁基板の側面
に設けた外部端子と、前記外部端子に接続して前記第1
の絶縁基板の下面及び第2の絶縁基板の上面に設けたパ
ッドと、前記素子搭載部に搭載して前記内部端子に電気
的に接続したICチップと、前記ICチップを含んで前
記開口部内のみを封止した封止樹脂とを有することを特
徴とするリードレスチップキャリア。
1. A first insulating substrate having an element mounting part in the center and internal terminals arranged around the element mounting part; and a first insulating substrate having an opening corresponding to the element mounting part. a second insulating substrate provided on and integrated with the first insulating substrate; an external terminal connected to the internal terminal and provided on the side surface of the first and second insulating substrate; and an external terminal connected to the external terminal. Said first
pads provided on the lower surface of the insulating substrate and the upper surface of the second insulating substrate; an IC chip mounted on the element mounting portion and electrically connected to the internal terminal; and only the inside of the opening including the IC chip. A leadless chip carrier characterized by having a sealing resin sealed with.
JP3028481A 1991-02-22 1991-02-22 Leadless chip carrier Pending JPH04267361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3028481A JPH04267361A (en) 1991-02-22 1991-02-22 Leadless chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3028481A JPH04267361A (en) 1991-02-22 1991-02-22 Leadless chip carrier

Publications (1)

Publication Number Publication Date
JPH04267361A true JPH04267361A (en) 1992-09-22

Family

ID=12249850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3028481A Pending JPH04267361A (en) 1991-02-22 1991-02-22 Leadless chip carrier

Country Status (1)

Country Link
JP (1) JPH04267361A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738009A (en) * 1993-06-25 1995-02-07 Matsushita Electric Works Ltd Chip carrier
US5723901A (en) * 1994-12-13 1998-03-03 Kabushiki Kaisha Toshiba Stacked semiconductor device having peripheral through holes
KR100240748B1 (en) * 1996-12-30 2000-01-15 윤종용 Semiconductor chip package having substrate and manufacturing method thereof, and stack package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61247060A (en) * 1985-04-24 1986-11-04 Nec Corp Leadless chip carrier
US4956694A (en) * 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61247060A (en) * 1985-04-24 1986-11-04 Nec Corp Leadless chip carrier
US4956694A (en) * 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738009A (en) * 1993-06-25 1995-02-07 Matsushita Electric Works Ltd Chip carrier
US5723901A (en) * 1994-12-13 1998-03-03 Kabushiki Kaisha Toshiba Stacked semiconductor device having peripheral through holes
KR100240748B1 (en) * 1996-12-30 2000-01-15 윤종용 Semiconductor chip package having substrate and manufacturing method thereof, and stack package
US6861737B1 (en) * 1996-12-30 2005-03-01 Samsung Electronics Co., Ltd. Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same

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Effective date: 19970114