JPS6170482A - Ultrasonic detecting and displaying method - Google Patents

Abstract

PURPOSE:To display past and current information on a CRT simultaneously by forming at least one main memory for storing the information of one picture on the CRT and always displaying the held data fixedly on a part of the CRT. CONSTITUTION:In an ultrasonic detector for a fish finder or the like, a receiving signal detected by a transmitter/receiver 23 is converted by an A/D converter 28 and the digital signal is written in a signal input memory 34. A reading signal from a main memory 81 is supplied to a CRT 82 through a color con verter 177. Shift register F1-Fn corresponding to line scanners Ll-Ln on the display surface of the CRT 82 are formed in the main memory 81. Every trans fer of data from the memory 34 to the main memory 81, the up-to-date data are displayed on the line scanner L1 and the oldest data are transferred to a delay shift register 124 and removed from the main memory 81. Therefore, the display lines on the CRT 82 are shifted to the older lines one by one in the rectangular direction to these lines. Consequently, oscillation lines 155 corre sponding to oscillation pulses, a display 153 corresponding to the sea bottom and a display 154 corresponding to a school of fish appear on the display surface of the CRT 82 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic detection and display method, such as a fish finder, which emits ultrasonic pulses and displays the reflected waves.

Such an ultrasonic detection and display method is disclosed in, for example, Japanese Patent Application No. 1983-
14424 "Color Group Detector".

In this conventional ultrasonic detection display device, for example, the oldest information is displayed at one end of the cathode ray tube, and the newest information is displayed at the opposite end as one display line for each detection information. Each time information is entered, the display of the oldest information is erased so that new information is always displayed at a predetermined end. In that case, if the supply of the new information is stopped, the old information stored up to that point will be permanently displayed as a still image for one screen. By the way, by comparing current information with past information, it is possible to make more accurate analyzes of new information.For example, when a fishing boat moves while detecting schools of fish with a fish finder, If you see a school of fish by looking at the detection information display, you have already passed the position of that school of fish, and you must return to the original position to catch the school of fish. In order to do this, information about the vicinity where the image of the school of fish was captured is stored in advance, and the display of information indicating the school of fish and its vicinity is compared with the current detection information display as it approaches the color school. It becomes possible to catch the school of fish easily. It would be extremely convenient if past information could be stored in this way and compared and displayed with current detection information.

An object of the present invention is to provide an ultrasonic detection and display method that allows past information and current information to be displayed simultaneously on the same display screen.

According to the present invention, a scanning display to display the display,
For example, at least one main memory that stores information for one screen of a cathode ray tube is provided, and the contents of the main memory are retained even when new information is input manually, so that the retained data is always stored in the cathode ray tube. A means is provided for displaying the information in a fixed manner in part. On the other hand, a display section is provided in another section of the cathode ray tube in which old data disappears when new information is transferred.

Next, an example in which the ultrasonic detection and display method according to the present invention is applied to a fish finder will be explained with reference to the drawings.

A transducer 23 is excited at a constant cycle from a transmitting section 1 in a transmitting/receiving section 11 of a fish finder through a transmitting/receiving circuit 2. As a result, ultrasonic pulses from the transducer 23 are radiated toward the seabed 3. The reflected wave is received by the transducer 23 and received by the receiver 4 through the transmitter/receiver circuit 2. This received signal consists of a transmitted pulse 25, a reflected signal 26 from the fish school 5, a reflected signal 27 from the seabed 3, etc., as shown in FIG. 2A. This received signal is converted into, for example, a 4-bit digital signal by the AD converter 28, and the digital signal is written into the signal acquisition memory 34. The signal acquisition memory 34 is, for example, a shift register, and the AD converter 2
It is possible to simultaneously write as many digital signals as the number of output parallel bits. In this writing, a write pulse (FIG. 2B) generated in the write pulse generation circuit 6 from a signal of an oscillator (not shown) in the transmitting section l is sent to the OR circuit 56.
The signal is supplied to the memory 34 through the memory 34 for processing.

On the other hand, a color cathode ray tube display 82 is provided, and the display surface of this display 82 is scanned by an electron beam controlled by a line synchronization signal and a surface synchronization signal from the cathode ray tube control circuit 7. The read signal from the main memory 81 is sent to the color converter 17.
7 to the display 82. The main memory 81 is composed of, for example, a shift register and has a capacity to store the sentiment of one screen on the display surface of the display device 82, and for easy understanding, the line scanning line f I+ j! on the display surface of the display device 82 is stored. ,,・
・Corresponding to ln, shift register sections F,,F,,...
- There is Fn, and these register sections are sequentially connected in cascade. At the time when register parts F,, Ft,...
Each digital signal in Fn is connected to scanning line 11+x
, . . . are displayed on In. shift register section F,
The output from the latter stage is supplied to the color converter 177 and fed back to the first stage of the first shift register section Fn through the gate circuit 8. Selected.

In this state, the contents of the main memory 8■ are displayed on the display 82 as a still image. Shift register section F, =Fn
Each stage can store 4-bit digital signals in parallel. The color converter 177 performs signal conversion to cause the display 82 to emit light in a predetermined color according to the level of the signal in response to the manually inputted digital signal, and its output causes the color cathode ray tube display 82 to emit light. Red, green, and blue electron guns are controlled.

In the transmitting/receiving section 11, a received signal corresponding to one transmission pulse is captured into a data capture memory 34, and the signal in this memory 34 is transferred to the main memory 81 as information of one display line. This new signal is then displayed at a predetermined position on the display.

For example, in the figure, at the beginning of surface scanning, the first line scanning line l.

The newest signal is read out from the register section F and displayed. The data that was in the register F8 at the beginning of surface scanning is read out and displayed on the second wA scanning line 12. Similarly, the oldest data present in the register section Fn at the beginning of surface scanning is displayed on the first scanning line ff1n. The data acquisition memory 34 has the same capacity as one of the shift register sections F1 to Fn of the main memory 81. When writing to the memory 34 is completed, a signal indicating this is supplied to the read pulse generation circuit 9. This circuit 9 is supplied with a surface synchronization signal Pv and a line synchronization signal P shown in FIG. 2C from the control circuit 7. A read pulse is generated for the IVA synchronization signal cycle as shown in the second diagram from the next surface synchronization signal after the write is completed. The read pulses are synchronized with the shift pulses of the main memory 81 and are the same number as the write pulses. The read pulse reads the acquisition memory 34 through the OR circuit 56, and its output is supplied through the gate circuit 8 to the first stage of the shift register Fn. The output of the main memory 81 is also constantly supplied to the shift register 124 for delaying one scanning line. Therefore, when the transfer is completed, the newest data previously stored in the register section Fl is in the register 124, and in this state the output of the main memory 81 is returned to the first stage shift register section Fn through the soft register 124. The feedback through the delay shift register 124 is a period from the end of reading from the memory 34 until the next surface synchronization signal, as shown in FIG.

This plane distance is 8M (immediately before the r issue, the current capture memory 34
The newest data written from shift register section F
1 and the oldest data up to that point is the gate circuit 8 so that the output of the main memory 81 is fed back to the shift register section Fn when the main memory is read from the 0th order surface synchronization signal located in the soft register 124. is controlled. In this way, new data is written to the main memory 81,
The oldest data is removed from main memory 81 while remaining in shift register 124.

Each time data is transferred from memory 34 to main memory 81 in this manner, the newest data is transferred to line scan fir!
, the oldest data is removed from the main memory 81, and the display line moves one by one in the direction perpendicular to that line on the display surface, and the second newest data moves above the line scanning line l. will be displayed. As a result, an oscillation line 155 corresponding to the oscillation pulse 25, a display 153 corresponding to the seabed 3, and a display 154 corresponding to the school of fish 5 appear on the display surface of the display 82, respectively. In other words, a display similar to the record on the record paper of a conventional fish finder is obtained, and the display moves from right to left in the same way as when the record paper is moved from right to left in FIG. In addition, in FIG. 1, the speed of received data from the transceiver 11, the scanning speed of the cathode ray tube display 82,
is selected appropriately, the data acquisition memory 34 is omitted and the data from the 32nd day of AD conversion is directly stored in the main memory 81.
It is also possible to write to.

Next, the fish finder according to the present invention will be explained in more detail with reference to the drawings from FIG. 3 onwards. Figures 3 to 5 are divided into parts that should originally be shown as a single drawing, and the symbols in circles attached to the ends of each lead wire indicate that the same wires are connected to each other. ing. In FIG. 3, the transmitting/receiving section 11 is almost the same as that of a conventional fish finder. That is, the reference signal from the reference oscillator 12 is frequency-divided by the range frequency divider 13, and the frequency division ratio is determined by the range switch 1.
Changed by selection 4. In other words, the detection range is, for example, Oml OOm, O-200m, 0~400m5O~8
The frequency division ratio of the frequency divider 13 is changed depending on the setting, such as 00 m, and the deeper the search is performed, the higher the frequency division ratio is and the lower the output frequency is.

The output frequency-divided in this way is output to the display time switching circuit 15.
For example, one of three frequency division ratios is selected: the standard one, its double, and the standard 4. This circuit is specially designed for a fish finder using this shaded Ti striped tube, and by selecting the three-point changeover switch 16, the normal display is displayed when it is in one switching position, and when it is in the other one switching position. The time is displayed in fast forward mode, and the output frequency is doubled, and when the time is in another switching position, the display is in slow mode, and the output frequency is twice that of the normal display.
It is said that In other words, the changeover switch 16 speeds up or slows down the rewriting time of information in the main memory 81 that stores display information for the cathode ray tube display 82, which will be described later.
It can be switched with .

The output of the display time switching circuit 15 is the repetition period counter 17.
The frequency is further divided by , thereby creating a trigger oscillation period. The output of this repetition period counter 17 is shown, for example, in FIG. 6A, and this output is differentiated by a differentiating circuit 18, and, for example, its rising pulse (FIG. 6B) is extracted. This rising repulse lasts for a time equal to the propagation time of the ultrasonic pulse at a depth below the water surface to which the transmission/reception wave 2S23 is attached in the stuttering correction circuit 19 consisting of a monostable multi-vibration, that is, as shown in No. 6 [1111C]. It is converted into a pulse of time TI. The converted output is supplied to the transmission trigger generation circuit 21, and the differential pulse (
A trigger signal delayed by time T1 is obtained from FIG. 6B).

This trigger signal drives the transmitter 22, and its output excites the transducer 23, which emits ultrasonic pulses toward the seabed. Based on the transmission of this ultrasonic pulse, the reflected signal is received by the transducer 23, and the reflected signal is received by the receiver 2.
For example, as shown in FIG. 4, an oscillation pulse 25, a reflected signal 26 from a school of fish, and a seabed reflected signal 27 are received.

The output of the receiver 24 is outputted by an AD converter 28, for example, into four
The data is converted into a Pinto digital camera No. 3 and supplied to each of the plurality of data acquisition units.

The data importing section is a normal display data importing section 31.
When a partial enlarged display data import unit 32 and a seabed enlarged display data import unit 33 are provided, the data import memory 34.35.3 of these data import units 31.32.33
6 are supplied with the outputs of the AD converters 28, respectively.

In the 13'ij1 display data acquisition section 31, the gate signal generation circuit 50 is driven by the pulse from the differentiating circuit 18 as shown in FIG. 6F, and a gate signal is generated.
The shift pulse counter 49 starts a coefficient operation under the control of this gate signal, and the output pulses of the range frequency dividing circuit 13 are counted by this counter 49. counter 4
The coefficient value of 9 is decoded by a decoder 51, and the output terminals of the decoder at appropriate intervals are shifted and selected by a selection switch 52.
Select with . The selection fixed terminal of the decoder 51 of the shift selection switch 52 is, for example, 5 in terms of ultrasonic detection distance.
Pulses Ps whose phases are sequentially shifted by 0m are obtained as shown in FIG. (A gate signal is generated as shown in (). For example, when the range switch 14 is
When the second largest pulse is selected by the switch 52 with the setting set to , the water depth range from 50 m to 150 m will be detected. The shift pulse counter 49 counts a predetermined number, and from the time when the counter 49 reaches full count until the next trigger pulse is generated, at least one
A time corresponding to the shift distance, in this example 100 m, is generated. This full count output stops the sending of the gate signal from the gate signal generating circuit 50, and as shown in FIG. 6F, the output becomes low and the counting operation of the counter 49 is stopped. The gate signal generation circuit 50 is a flip-flop circuit, for example, and is set by the output of the differentiating circuit 18 and reset by the output of the counter 49. Other gate signal generation circuits are also constructed in the same manner as this gate signal generation circuit 5°.

When the output of the gate signal generation circuit 53 becomes a high level, the frequency dividing circuit 54 and the data acquisition counter 55 are activated, and the frequency dividing circuit 54 further divides the frequency of the range frequency dividing circuit 13. The output is counted by a data acquisition counter 55. Further, the output of the frequency dividing circuit 54 is applied to the data acquisition memory 34 through an OR circuit 56, and the output of the AD converter 28 is written into the memory 34 through an OR circuit 57 for each pulse. This counter 5
5 is the number of pixels in one display line on the display 82, for example, 256, which is the full count, and the gate signal generation circuit 53 is controlled by its output, and its output becomes low level. Therefore, the operations of the frequency dividing circuit 54 and the counter 55 are stopped. In other words, the frequency dividing circuit 54 generates a data acquisition pulse as shown in FIG.
Data for each item is imported.

In the partial enlargement display data acquisition section 32, the counter 5
5 is operating, that is, the normal display data acquisition section 3
In order to select and enlarge an arbitrary section while data is being captured in 1, the count contents of the counter 55 are supplied to the decoder 5, and each output terminal of the decoder 58 is set to 1 by the enlargement position selection switch 59. For example, the section of the output gate signal of the selection gate signal generation circuit 53 is divided into five equal parts, and the pulses whose phase is sequentially shifted corresponding to one of the five equal parts are sent to the five fixed terminals of the selection switch 59. to the 6th
The pulses are obtained as shown in FIG. J, and one of the pulses is selected by switch 59. This selected pulse causes the output of the gate signal generation circuit 61 to go to a high level as shown in FIG. Frequency divider circuit 6
The output pulse from the reference oscillator 12 is supplied to the frequency divider circuit 62, and the frequency division ratio is changed by the expansion width selection switch 64. The frequency ratio is small so that a high frequency output can be obtained.This pulse is counted by the data acquisition counter 63 and drives the data acquisition memory 35 through the OR circuit 65, and the output of the AD converter 28 is output from the OR gate. 67 into the memory 35.

The counter 63, like the counter 55, reaches a full count at 256 bits, for example, and the gate signal generation circuit 61 is controlled by its full count output, its output goes low and becomes healthy, and both the frequency divider circuit 62 and counter 63 become inactive. Become. In this way, while the output of the gate signal generating circuit 61 (K in FIG. 6) is high, the A of the corresponding received signal is
The D-converted output is read into the memory 35 as 256 sample information, that is, as pixel information of one display line segment.

In the bottom enlarged display data acquisition section 33, the differentiation circuit 18
The gate signal generation circuit 68 is driven by the differential pulse shown in FIG. 6B from 0 frequency division circuit 69, and the frequency division circuit 69 is activated by this output signal (FIG. 6L).
When attempting to significantly expand the frequency of the reference signal from the oscillator 12, similar to the divide-by-6 circuit 62, the frequency division ratio is changed according to the expansion rate set by the expansion width selection switch 71. The output of the divide-by-1 circuit 69, which outputs high-speed pulses with a small frequency division ratio, drives the data acquisition memory 36 through an OR circuit 72, and the output of the AD converter 28 is read for each pulse. The capacity of this memory 36 is the same as that of memories 34 and 35, so it is full with 256 pulses, but if more data is written than this, the oldest data is written every time new data is written. They disappear one after another.

On the other hand, the output of the receiver 24 is also supplied to a bottom signal detection circuit 73, and a conventionally known circuit can be used as this circuit 73. A signal larger than the level is detected as a bottom signal. This bottom signal is a pulse as shown in FIG. Data acquisition operations are also stopped. The latest data captured at this time is the signal reflected from the ocean floor.

Since such data is always captured, the seabed is always at a fixed position on the display line, the seabed line is displayed as a straight line, and the portion above the seafloor is enlarged and displayed according to the frequency division ratio of the frequency divider 69.

The data fetched into the data fetching memories 34, 35, and 36 of the data fetching section as described above is stored in the common buffer memory 79 according to the selection state of the selective reading means 74 to 76 provided correspondingly. Data is imported into. The data taken into this buffer memory 79 is transferred to a main memory 81, and the main memory 81 is repeatedly read out and supplied to a cathode ray tube display 82 to be displayed as an image.

Control of the cathode ray tube display 82 is performed as follows.The output signal from the 0 oscillator 83 is divided by the frequency division circuit 84 to the line (horizontal) scanning period of the cathode ray tube display 82.
Its output is supplied to a line synchronization signal generation circuit 85, and this output is supplied to a display 82. The output of the frequency divider 84 is also supplied to a plane (vertical) sync signal generator 86 which divides the frequency to produce a plane sync signal, which is supplied to the display 82. Information corresponding to one display line of this display 82 is stored in the buffer memory 79, and information for that one display line is transferred to the main memory 81 as described above.

The data from the data import section is transferred to the buffer memory IJ79 using the clock of the display 82 as a reference.

Therefore, the output of the data acquisition counter 55 and the output pulse of the plane sync signal generation circuit 86 are supplied to the sync selection circuit 87. This plane sync pulse signal is, for example, the one shown in FIG.
The selection is made as shown in FIG.

The gate signal generation circuit 88 is driven by this selected plane synchronization pulse, and the circuit 88 generates a signal as shown in FIG. The line scanning frequency signal from the frequency dividing circuit 84 is supplied to the zero frequency dividing circuit 89, and the frequency dividing ratio of this frequency dividing circuit 89 is changed by selecting the display width selection switch 92.

The switch 92 has four fixed terminals, for example a to d, and when connected to a, the frequency division ratio of the frequency divider circuit 89 is 1/8, and when connected to b, the frequency division ratio is set to 1/8. is 1/
4. When connected to C, the frequency division ratio is set to A; when connected to d, it is not connected to the frequency dividing circuit 89 and this selective reading means is not selected. Each negative output of fixed terminals a to c is supplied to an OR circuit 93, and the gate signal generation circuit 88 is cleared by the output, and the output of the circuit 88 is held at a low level. When selected, the selected data is displayed as one display line on the display 82, that is, it is displayed over the entire width of the display, and when the terminal is selected, the selected data is displayed as one display line on the display 82.
, and if terminal C is selected, it operates so that it is displayed in the width of x.

The frequency divided output of the frequency dividing circuit 89 is counted by a read counter 91, and this counter 91 reaches a full count with 256 pulses, similar to the data acquisition counter 55 and the like. As mentioned above, the display width selection switch 92 also serves as a switch for selecting or not selecting the selective reading means.
2 is located at terminal d, this selective reading means is not selected, and the output of the gate signal generating circuit 88 does not go to high level. However, when the selective reading means is selected, the switch 92 is located at terminal a. "-c, a frequency divided output is obtained from the frequency dividing circuit 89, and not only is this output pulse counted by the counter 91, but also the selective reading means 74 and the corresponding data acquisition memory 34 are It is driven, data is read from it, and the read data is supplied to buffer memory 79 through OR gate 94.

Writing to buffer memory 79 is performed in synchronization with the slowest pulse among the output pulses of frequency divider circuit 89. ! The pulse from the p-frequency divider circuit 84 is divided into 1/8 by the frequency divider circuit 95, and the divided output is supplied to the buffer memory 79 through the OR circuit 96, and under its control, the data from the OR circuit 94 is The data is written to the buffer memory 79. Same to control this dent! tlI detection circuit 8
The output of 7 is also supplied to a gate signal generation circuit 97, which generates a gate signal as shown in FIG.
is in operation, the counter 98 counts the output of the frequency dividing circuit 95, and when it counts a predetermined number, 256 in this example, the gate signal generating circuit 97 is controlled by the output, and its output becomes low level.

The selective reading means 75 and 76 have almost the same configuration as the selective reading means 74, and therefore each gate signal generating circuit 8
Furthermore, a frequency dividing circuit 89, a readout counter 91, a display width selection switch 92, and an OR circuit 93 are provided, and these are connected in the same manner. A selection circuit 99 is provided in place of the synchronization detection circuit 87. i! The selection circuits 99 of the i-translation reading means 75 to 76 are sequentially connected in cascade, and the synchronization detection circuit 87 is connected at the preceding stage. Further, the output of the OR circuit 93 is supplied to the next stage selection circuit 99 via the impark 101, and the output of the counter 91 indicating that reading has ended and the output of the gate signal generation circuit 8 are also supplied to the next stage selection circuit 99. 1 is supplied to circuit 99.

As shown in FIG.
When the output of 01 is at a low level, that is, when the display width selection switch 92 in the previous stage is connected to any of the terminals a to C, the gate IO2 is closed, so that the synchronization detection circuit of the selection reading means in the previous stage 87 or the output of selection circuit 99 cannot pass through gate 102. However, when the display width selection switch is selected at the terminal d, that is, when the selective reading means is not selected, the output of the inverter 101 of the selective reading means becomes high level.
The gate 102 is opened, and in the case of the selection circuit 99 in the previous stage or the selection reading means 75, the activation signal from the synchronization detection circuit 87 passes through the gate 102 and further passes through the OR gate 103 to become the output of the selection circuit 99.

On the other hand, when the display width selection switch 92 selects one of the terminals a''-c, the gate 102 is closed as described above, and the gates 1-104 are opened by the output of the gate signal generation circuit 88 at the previous stage. The last output pulse of the read counter 91 is outputted through the gate 104 and further through the OR gate 103.In other words, when the selective reading means is not selected, the activation signal from the previous stage is sent to the next stage through the gates 102 and 103. When the display width selection switch 92 is set to one of terminals a to c, the full count output of the read counter 91 is supplied to the next stage as a starting signal.

For example, the activation signal is given as shown in FIG. Assuming that the frequency division ratio of the circuit 89 is the largest, the readout counter 91 reaches a full count, and the gate signal from the gate signal generation circuit 88 ends as shown in the 81st page, the display width selection switch 92 is connected to the terminal. In this case, the frequency division ratio of the frequency divider circuit 89 is V, so that the output frequency of the switch 92 is
Therefore, the output of the counter 91 reaches the full count at twice the speed, and the output width of the gate signal generation circuit 88 becomes A and A in FIG. 8B, as shown in FIG. 8C. Become.

Now, in the selection readout means 74, the switch 92 is set to terminal C, and in the selection readout means 75, the selection switch 92 is set to terminal C! #If it is controlled, the full count output of the preceding stage counter 91 passes through the gate 104 of the selection circuit 99 of the selection reading means 75, and the output of the gate signal generation circuit 88 rises as shown in the eighth figure.
Since the frequency division ratio of the frequency dividing circuit 89 is set to A, the counter 91 of the selective reading means 75 reaches a full count at twice the counting speed of the reading counter 91 of the selective reading means 74 at this time. As shown in Figure 8, the output signal of the gate signal generation circuit 8 becomes low level. When the selection reading means 76 is driven at the end of this signal and its display width selection switch 92 is set to terminal C, its gate (No. Output.

As described above, the frequency dividing circuit 95 is selected to have the highest frequency division ratio in the frequency dividing circuit 89, and the full count of the counter 98 is selected to be the same as that of the counter 91, so that the write time to the buffer memory 79 is is the same as the length of the gate signal when the selection switch 92 shown in FIG. 8B is set to the full width terminal a. Therefore, if the display width selection switches 92 of the selective reading means 74, 75.76 are set to terminals A, C, and C, respectively, the respective gate signal generating circuits 88 of the selective reading means 74, 75. , D, and E occur, and during these periods the corresponding data acquisition memories 34 .
35 and 36 data are respectively read out and written into the buffer memory 79. The contents of the memory 34 are stored in the buffer memory 79 as shown in FIG.
05, and each content of memory 35.36 is written as part 106.107 of χ, respectively.

In reality, each of the memories 34 to 36.79 has the same capacity, so data is written to the buffer memory 79 with data being skipped depending on the compression ratio when writing to the buffer memory 79.

The display device 82 thus transferred to the buffer memory 79
The information on one display line segment is transferred to the main memory 81. The main memo U 81 is, for example, a shift recorder having a capacity equivalent to one screen of the cathode ray tube display 82. The output of the oscillator 83 is given to the clock generator 111 , and the main memory 81 is softened by the clock from the clock generator 111 .The output is supplied to the cathode 1-ray tube display 82 , and is also sent to the main memory 81 through the gate 112 and the OR gate 113 . will be returned to. In this example, one scanning line of the cathode ray tube display 82 is used as one display line, and when the data from the data acquisition section is transferred to the buffer memory 79, the counter 98 reaches a full count and the output is (FIG. 11A) is also applied to the gate signal generator 114, from which a gate signal is obtained as shown in FIG. 99B. Game by this signal)
115 is opened to allow the output of buffer memory 79 to be supplied to main memory 81 through gate 115.113. The frequency dividing circuit 116 and the counter 117 are controlled by the gate signal from the gate signal generating circuit +14.
is in an operating state, and the output of the oscillator 83 is divided by the frequency dividing circuit 116 to obtain a clock signal having the same speed as the clock signal of the clock generator 111. It is sequentially applied as a read clock for the buffer memory 79.

Therefore, the read clock from buffer memory 79 and the write clock of main memory 81 are synchronized.

When the counter 117 counts pixels for one scanning line, 256 in this example, the count becomes full and the gate signal generation circuit 114 is controlled, its output becomes low level, and the frequency dividing circuit 116 and counter 117 operate. stops. The output of the counter 98 is also supplied to the gate signal generation circuit 118, and this output becomes a high level as shown in FIG. The signals are counted by this counter 119. Counter 119 is display 2
When the number of line scanning lines on one screen of 382 is counted, a full count is reached, and the output of the gate signal generation circuit 118 becomes low level, and the operation of the counter 119 is also stopped. Therefore, a high level output having a length of one screen as shown in FIG. 9C can be obtained from the gate signal generating circuit 118.

A circuit 122 performs an AND operation between this and the output shown in FIG. 9B of the gate signal generating circuit 114 which is inverted by an inverter 121, thereby obtaining the signal shown in FIG. This signal opens the gate 123,
The output of the main memory 81 is fed back to the main memory 81 through a delay circuit 124 for one scanning line, and further through gates 303, 304, and 123, 113 in sequence.

When new information is input to the main memory 81 from the buffer memory 79 in this way, the newest information in the king memory 81 up to that point is returned to the main memory 81 with a delay of one scanning line by the delay circuit 124. become. The gate circuit 123 closes one pixel scanning period after the gate circuit 115 opens, that is, after the transfer of information from the buffer memory 79 to the king memory begins. Therefore, when the information in the buffer memory 79 is transferred to the main memory 81, the information on the oldest display line is transferred to the delay circuit 124 and erased from the main memory 81. The gate circuit 112 is supplied with a signal shown in the 91st line obtained by inverting the output of the gate signal generating circuit 118 by an inverter 125, and is applied to the gate circuit 112 during periods other than the area scanning period during which information is transferred from the buffer 7 memory 79 to the main memory 81. is gate 112
only is open. In addition, the surface synchronization signal and the line synchronization signal are supplied to the lock generator 111, and the generation of the clock signal is stopped in the electron beam retrace section of the display 82.

Next, check the various display states of the fish finder mentioned above.
Let us explain its operation with reference to the figure. In FIG. 10, the line scanning direction of the display 82 is the vertical direction, and the rightmost position 151 is the display position of the newest information.
The oldest fI4Ifu is displayed at position 152 on the leftmost side. In contrast to the display on the far right of this display screen, the oldest display on the left is information from 30 minutes ago.
0 m and only the selection reading means 74 is selected, and a seabed display 153, a school of fish display 154, and an oscillation line 155 appear. Depth scale 156 is 1 in the figure.
Displayed every 00m. Furthermore, at the bottom of the display screen, a time scale 157 is displayed as a dot every two minutes, for example.6 In the display of FIG.
Display of detection information in the range of 0 to 800m 9 minutes ago,
This is a case where the enlarged display of the 400 to 500 m portion is displayed in parallel. The enlargement range 400 to 5 (10 is selected by selecting the output of the decoder 58 with the enlargement value i! stream switch 59, and the enlargement width of 100 m is selected by the switch 64. Selection reading means, stages 74 and 75 1! translation reading means 74, 75 so that these displays are displayed on the upper half and lower half of the display screen, respectively.
In this case, the display width selection switch 92 is set to the terminal.

In this case, the acquisition memory 34 contains information from 0 to Room! as in the previous case. is taken in as one display line segment, and a portion of 400 to 500 m is taken into the memory 35 as one display line segment. i! The contents of the memory 34 are compressed by the Elf output means 74 and written into the first half of the buffer memory 79, the right half in the figure, and the contents of the memo 1J35 are compressed and taken into the second half. Therefore, as shown in Figure 10, the sea floor is 161
, a school of fish is displayed as 162, and its enlarged view is further displayed as a seabed 163 and a school of fish 164. The depth scale 156 is compressed and displayed as a depth scale 160.

Further, the output of the gate signal generation circuit 61 indicating the enlarged position is supplied to the enlarged mark generator 170, and the output of the gate signal generation circuit 61 corresponding to the display color (for example, white) is supplied to the enlarged mark generator 170 at the position corresponding to the rising and falling edges of the gate signal of the gate signal generating circuit 61. The resulting digital signal is taken into the data take-in memory 34 through the OR circuit 57. As a result, an enlarged position display line 165 indicating the enlarged position is displayed, indicating that this portion is enlarged downward. Further, the output of the gate signal generation circuit 61 operates the enlarged depth mark generator 166, which divides the output of the frequency divider 13 and generates a depth mark for the enlarged display portion. It is written into the enlarged information acquisition memory 35 through the OR circuit 67 as a digital signal indicating the level corresponding to the displayed color.

As a result, an enlarged depth mark 167 is displayed on the display.

Also, in order to add a border line 168 indicating the boundary between the normal i[11 display in the upper half and the enlarged display in the lower half, i! The output of the output counter 91 of the selection reading means 74 is written to the buffer memory 79 through the OR circuit 169 and further through the OR circuit 94. Similarly, when the selective reading means 74 to 77, etc. are selected, the output of the reading counter 91 of the selective reading means is supplied to the OR circuit 169, and the signal indicating the boundary of the display is used as a boundary line signal. The data is written to the buffer memory 79.

Furthermore, in this example, 11 minutes before the current time, tif
This is a case where the fi display is left unchanged, the enlargement switch 64 is selected, the enlargement rate is set to dog, the width is enlarged to 50 m, and the enlargement position selection switch 59 is selected to enlarge the area between 550 m and 600 m.

Next, we will explain the most VF characteristic of this invention, where an old image is fixedly displayed in a part of the display screen, and the oldest information is sequentially removed while displaying new information in other parts. do. By selecting only the selection reading means 74, for example, as shown in FIG. A respective outgoing line display 15.5 appears. This image is taken when the fishing boat 201 passes through the passage 202 and is at position (2) in FIG. 12, and a school of fish 203 is present on the passage 202. From this state of Fig. 11A, Fig. 11B to Fig. 11
As shown in the diagram, the vertical axis of the image in FIG. 11A is compressed to one half, and the lower half of the display screen is fixedly displayed as a fixed display section 204, while the upper half of the screen is displayed on a moving display section 205.
The display is such that the oldest data is sequentially removed each time new data is obtained. FIG. 11B is an image when the fishing boat 201 is at the position ■ of the passage 202, and the moving display section 2
The fish school image No. 05 moves to the left with respect to the fixed display section 204, that is, to the older side. When the fishing boat 201 reaches position ■, the image of the school of fish disappears, and the fishing boat 201 appears near the school of fish 203 based on the situation of the seabed line.
I understand that it has arrived. In the 11th diagram, the image on the movable display section 205 is almost the same as the image on the fixed display section 204, and is located at almost the same position (■) as the image on the fixed display section 204. a
It is shown that ship 201 has come again. Therefore, while looking at the images on the fixed display section 204 and the movable display section 205,
The fishing boat 201 can be reliably brought close to 3.

To display the display shown in FIG. 11, turn off the normal fixed changeover switch 206 in FIG. 5, and first reduce the display in FIG. The contents of the main memory 81 are rewritten so that they are compressed and displayed in two directions, one above the other. That is, the fixed-movement simultaneous display control circuit 207 operates, and the terminal IK of the control circuit 207 becomes high level from the end of the surface synchronization signal immediately after the switch 206 is turned off.
This is applied to the gate 208 and the inverter 20
9 to gate 301. Therefore, the read clock when reading information from the buffer memory 79 and supplying it to the main memory 81 is not the output of the frequency dividing circuit 116, but
The clock from the frequency divider circuit 211, which has a frequency division ratio of 1/2 of the frequency division ratio of this circuit and outputs a clock twice as fast as the output clock of the frequency divider circuit 116, is applied to the gate 208.302°98. The signals are sequentially passed through and applied to the buffer memory 79. Therefore, during the first half of the line scanning period, the buffer memory 79 is read out, and the information is read into the main memory 81 at the speed of the frequency divider circuit 111, that is, the speed of the cathode ray tube display 82.

■s of the 13th A- is the surface scanning section immediately after the fixed changeover switch 206 is turned off, H3 is the line synchronization signal, and the line scanning period between the above Vs immediately after the switch 206 is turned off. If we name them sequentially as H,, H□, H3,..., we get line scanning! Between IJ1 and 1 (in 1, from the terminals IF and IG of the control circuit 207 to the clock generator lit
A clock α having a speed of two times that of the clock is applied as a not pulse to the shift registers 212 and 213, respectively, as shown in FIGS. 13F and 13G. Therefore, when new information from the buffer memory 79 is written to the main memory 81, the newest data read from the main memory 81 until then is stored in the shift register 212.2.
13 respectively. These shift registers 21
The number of shift stages from 2 to 215 is selected to be 128, which is half of the number of shift stages of the shift register 124, 256.

In the next line scanning period H2, the terminal I of the control circuit 207
The clock α from H, 11 is applied to the shift registers 214 and 215 as shown in FIG. 13 H1r, and the next new data read from the main memory 81 is simultaneously written into these registers. In the first half of H2, a clock β having the same speed as the clock of clock generation R'a 111 is applied to the terminal IF as shown in FIG. 13F, and at the same time, the gate signal shown in FIG. 13A from the terminal IA is applied The gate 216 is opened, and the data in the shift register 212 is fed back to the positive memory through the gates 216.304 and 128.113 in sequence. In the latter half of the 0 period H2, a clock β is applied from the terminal tC to the shift register 213. At the same time, the gate signal shown in FIG. 13B from terminal IB is applied to gate 21.
During the 0th line scanning period H3 in which the contents of the shift register 213 are fed back to the main memory 81 through the gate 217, a clock signal is generated from the terminals IF and IG, and in the first half, a clock signal β is applied to the terminal IH. Terminal IC
In the second half, the gate signal shown in FIG. 13C to the gate 21B is generated, the clock β is generated to the terminal II in the second half, and the gate signal shown in FIG. The data is fed back to the main memory 81 through the gates 218 and 219.In the same way, the data on each display line is displayed in the same way on the first half and the second half of the display line. It is rewritten to the main memory 81. If no new data arrives after being rewritten in this way, the gate 1
12 is opened and the contents of the main memory 81 are displayed as a still image, as shown in the 111th page.

From this state, as shown in FIG. 11B, C, and D, the fixed display section 204 displays the previous data in a fixed manner, and the movable display section 205 displays a display that erases old data every time new data is obtained. Gate 115.11 in Figure 5
2.123 may be controlled as follows. Part 1
As shown in Figure 5, the surface scanning period when writing new data vs.
, for the same-line interval Hs, in the case of normal display, the gate 11 is displayed as shown in FIG.
2.115.123 is controlled by the gate signal with the same number, but the display in Figures B, C, and D is changed so that the gate signal for gate 112.115.123 is shown with the same number in Figure 15B. Live memo of new data! In the first half of the first line scanning period H1 during the surface scanning period when moving to J81, open the game) 115 and move the moving display section 2 in the upper half of the display screen.
New data appears only in 05. In the second half of each line scanning period, the gate 112 is opened and the fixed display section 2 in the lower half of the screen is opened.
The data for 04 is stored in the main memory 81 without delay.
Since the image is returned to , it becomes a still image.

After the second line scanning period, games 1-123 are opened in the first half of each period, each delayed by one scanning line, and the display is moved one display line to the right to perform a moving display.

An example of the control circuit 207 is shown in FIG. switch 20
6 is applied to the J terminal and its inverted signal terminal of the JK flip-flop 231, and this is applied to the gate signal generation circuit 1.
Read at the trailing edge of the plane sync signal from 1B. Therefore, the Q output of the flip-flop 231 becomes high level, the flip-flop 233 in the next stage becomes active, the output of the gate 234 becomes high level, the flip-flop knobs 235 to 238 become active, and 1/128 Counter 239 is also activated, and terminal IE goes low, which is applied to gate 303 in FIG. 5, which closes. Line interval signal Hs from terminal 241
is divided in half by the flip-flop 235, and divided into two by the flip-flop 236 at the terminal 242.
The frequency is divided by 1/1, and this clock is divided into 1/23 clocks.
The frequency is divided into 1/28, and the divided output is a flip-flop.
The frequency is divided in half by block 238. Furi 2 bufurosob 2
The AND output of the Q output of 35 and the line jlJ] signal Hs is supplied to the flip-flop 7 237 and divided into 1/2. With these combinations of the output states of the buffer 7 blocks 235 to 238, the outputs shown in FIG. 13 are obtained at the terminals IA to IJ.

As previously described with respect to FIGS. 11B, C, and D, in order to display the fixed display section 204 and the movable display section 205 on the display screen of the cathode ray tube display 82, the gate signal shown in FIG. 15B is applied. All you have to do is let it happen. An example of the occurrence of these gates (No. 3 will be explained below. The terminals IA to ID in FIG.
As shown in FIGS. A to D, gate signals for the first half and the second half of each line scanning period are generated sequentially. Therefore, the gate signal shown in FIG. 15B can be easily obtained using the same method of generating these gate signals. That is, as shown in the lower left part of FIG. 5, the line interval signal Hs from the terminal 241 is frequency-divided in half by the flip-flop 301, and the Q and d outputs of the flip-flop 301 are output to the gates 302 and 30, respectively.
3, and the output of gate 302 is supplied to gates 304, 3
05, and the output of gate 303 is input to gate 306,
Manually powered to 307. On the other hand, the frequency of the clock signal from the terminal 242 is divided into 1/128 by a frequency dividing circuit 308, and the frequency of the divided output is divided by 1/2 by a flip-flop 309.

The Q and Q outputs of flip-flop 309 are provided to gates 305, 307 and 304, 306, respectively. Therefore, gate signals shown in FIGS. 13A to 13C are obtained at 304 to 307, respectively, as in the case of FIG. 14.

When the Q output of flip-flop 233 in FIG. 14 becomes high level, the Q output causes flip-flop 301 to
．． 309 and the frequency divider circuit 308 are cleared, and the operation is started. As explained with reference to FIG. 14, the switch 206 is turned off, and the next surface circumference i! from the write command En immediately after that is turned off. During the ll signal Vs, the output of the gate 234 becomes high level, and the same display is performed up and down. When the surface synchronization signal Vs arrives and the Q output of the flip-flop 233 becomes high, the flip-flops 301 to 309 and the frequency dividing circuit 308 in FIG. 5 start operating. gate 30
5. The output of 306 is connected to gate 1 through 311
15 and 123, gates 305 and 307 pass through OR gate 312, and further pass through OR gate 313 to gate 112. Therefore, at gate 115, the first
The signal 115 in FIG. 5A and the output of the OR gate 311 are ANDed, and the output becomes the signal 115 in FIG. 15B, and the gate 112 ANDs the signal 123 in FIG. is taken, and its output is the 15th
The signal becomes signal 123 in Figure B, and further the signal 112 in Figure 15A.
The AND of the output of the OR gate 312 is taken by the gate 112, and the signal 112 shown in FIG. 15B is output. When the switch 206 is on, the Q of the flip-flop 233 is
The output becomes a low level, the output is inverted by the impark 314, a high level "1" is always given to the gate 115. The output of the OR gate 312 is at a low level @0, and the operation in FIG. 5 is the same as when the gates 311 and 312 are not connected.

In the above description, a knot register is used as the king memory 81, but a random access memory may also be used. In this case, each address in the memory is associated with each pixel on the display screen, and when new data is to be input, it is read out sequentially, the necessary data is temporarily stored, the new data is written in the vacant area, and then displayed. In order to move the data, a part of the data can be read out, temporarily stored, and written again.

As described above, according to the present invention, past data can be fixedly displayed on a part of the display screen, and current data can be displayed on other parts of the display screen.
By comparing these image displays, it becomes easy to discover and reconfirm the object that caused the reflection.

[Brief explanation of drawings]

Fig. 1 is a professional diagram that simply shows an example of the ultrasonic detection and display method according to the present invention, Fig. 2 is a waveform diagram for explaining the operation of Fig. 1, and Figs. Specific examples of the ultrasonic detection and display method according to the invention are divided into these three figures.
The block diagram shown in FIG. 6 is a waveform diagram for explaining the operation of the embodiment shown in FIGS. 3 to 5, and FIG.
8 is a waveform diagram for explaining the operation of the selective reading means, FIG. 9 is a waveform diagram for explaining the operation of the gate control circuit for the king memory, and FIG. 10 is a diagram showing an example of a display by the ultrasonic detection display device according to the present invention, FIG. A diagram showing the relationship between the display in Figure 1I and the position of the fishing boat, Figure 13 is a waveform diagram for explaining the simultaneous movement and fixed display operations in the examples of Figures 3 to 5, and Figure 14 is a waveform diagram for explaining the movement and fixed simultaneous display operations in the examples of Figures 3 to 5. Figure 15 is a diagram showing an example of a hyperactive display control circuit. Figure 15 is a waveform diagram showing gate control i'B in various types of fixed and moving simultaneous display. 1
Encircle 2nd E −-+ 6th Q O 7th circle 8 Figure 11 Figure A B CDE
F GHI
J K L 11th M N OP student 1
20 ■ Figure 13

Claims (1)

[Claims] (1) The main memory is repeatedly read out in synchronization with the scanning of the display surface of the scanning display, and the main memory is capable of storing display information for one display screen of the scanning display, and the main memory is repeatedly read out in synchronization with the scanning of the display surface of the scanning display. The detected information is supplied to the scanning display as display information, and the detection information consisting of the reflected waves of the emitted ultrasonic pulses is converted into a digital signal, and the digital signal is temporarily written to a buffer memory. The amount of writing is the same as the number of pixels on one line scanning of the scanning type display, and after the writing is completed, the data is transferred to the main memory during the area scanning period of the scanning type display, and thereby the new detection is performed. Ultrasonic detection in which information forms one display line on a predetermined line scanning line on the display surface of a scanning display, and the screen is moved by sequentially moving other display lines toward the oldest. In the display method, the information read from the main memory while displaying the one detection information as a display line of one line scanning line is synchronized with the line scanning,
The first or second read speed is half the main memory read speed.
The second or first memory is written to the main memory at the same speed in synchronization with the reading of the main memory, and the image that has been displayed up to that point is displayed on the display screen in the direction of the display line. The compressed images are compressed to one half, the same two compressed images are arranged and displayed in the display line direction, and then the digital signals from the buffer memory are read out at twice the writing speed to the main memory. An ultrasonic detection and display method characterized by transferring the new detection information to the main memory and displaying new detection information only on one of the two images on the display screen and moving the screen.