JPS61116679A - Ultrasonic detection and display - Google Patents

Abstract

PURPOSE:To facilitate the discovery and reconfirmation of an object causing a reflection, by displaying the previous data stationarily at a part of a display screen while the current data is displayed at other parts. CONSTITUTION:An ultrasonic pulse from a transmitter/receiver 23to be excited with a transmitting section 1 is reflected on the sea bottom 3 to be received with the transmitter/receiver 23 and a received signal from a receiving section 4 is converted 28 into digital from analog to be written into a signal fetch memory 34. On the other hand, a signal read from a main memory 81 is fed to a CRT82 and a display surface of the CRT82 is scanned over the surface thereof with the control of an electron beam by a synchronous signal. New detection information forms one display line on the surface thereof 82 and other display lines are moved to the right sequentially. Then, the reading out from the main memory 81 is performed at a half speed and the 8image displayed on the CRT 82 is compressed to a half in the direction of the display line so that the same two images will be displayed. So, a digital signal from the memory 34 is read out at the speed twice the writing speed for the main memory 81 to be transferred thereto 18 and thus, new detection information is displayed on one of the two images on the display surface.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic detection and display method in which, for example, an angular group detector emits ultrasonic pulses and displays the reflected waves.

Such an ultrasonic detection and display method is disclosed in, for example, Japanese Patent Application No. 1983-
No. 14424, ``Fish Finder'', provides a detailed explanation.

In this conventional ultrasonic detection display device, for example, the oldest information is displayed at one end of the cathode ray tube, and the newest information is displayed at the opposite end as part of the display line for each detection information. Each time information is entered, the display of the oldest information is erased so that new information is always displayed at a predetermined end. In that case, if the supply of the new information is stopped, the old information stored up to that point will be permanently displayed as a still image for one screen. By the way, by comparing current information with past information, it is possible to make more accurate analyzes of new information.For example, when a fishing boat moves while detecting schools of fish with a fish finder, the detection information If you see a school of fish and find a school of fish, you have already passed the position of that school of fish and you must go back and catch that school of fish.In this case, make sure to return to the original position correctly. information about the vicinity where the image of the school of fish was captured is stored in advance, and by comparing the display of information indicating the school of fish and its vicinity with the current detection information display, you can move closer to the school. It becomes possible to catch schools of fish easily. It would be extremely convenient if past information could be stored in this way and compared and displayed with current detection information.

- An object of the present invention is to provide an ultrasonic detection and display method that allows past information and current information to be displayed simultaneously on the same display screen.

According to the present invention, a scanning display to display the display,
For example, at least one main memory that stores information for one screen of a cathode ray tube is provided, and the contents of the main memory are retained even if new information is input manually, so that the retained data is always displayed on the shadow ellipse. Means are provided for permanently displaying the part of the tube. On the other hand, a display part is provided in another part of the cathode [9] so that when new information is transferred, old data disappears.

Next, an example in which the ultrasonic detection and display method according to the present invention is applied to a fish finder will be explained with reference to the drawings.

A transducer 23 is excited at a constant cycle from a transmitting section 1 in a transmitting/receiving section 11 of a fish finder through a transmitting/receiving circuit 2. As a result, ultrasonic pulses from the transducer 23 are radiated toward the seabed 3. The reflected wave is received by the transducer 23 and is received by the receiver 4 through the transmitter/receiver circuit 2. This received signal consists of a transmitted pulse 25, a reflected signal 26 from the fish school 5, a reflected signal 27 from the seabed 3, etc., as shown in FIG. 2A. This received signal is converted into, for example, a 4-bit digital signal in the AD converter IA n 28, and the digital signal is written into the signal acquisition memory 34. The signal acquisition memory 34 is, for example, a shift register, and can simultaneously write as many digital signals as the parallel outputs of the AD converter 28 and the number of node outputs. This writing is performed by supplying a write pulse (FIG. 2B) generated by the write pulse generating circuit 6 from a signal from an oscillator (not shown) in the transmitter 1 to the memory 34 through the OR circuit 56.

On the other hand, a color cathode ray tube display 82 is provided, and the display surface of this display 82 is scanned by an electron beam controlled by a line synchronization signal and a surface synchronization signal from the cathode ray tube control circuit 7. The read signal from the main memory 81 is a color converter! 7
7 to the display 82. The main memory 81 is made up of, for example, a knot register, and has a capacity to store information on one screen of the display surface of the display device 82, and has a capacity to store information on one screen of the display surface of the display device 82, so that it can be easily understood by scanning lines on the display surface of the display device 82! ! i1). 12. ...
1! The shift register section F l+F ! corresponds to n.
+...Fn, these register parts are sequentially '4t1
connected continuously. At the time when register part F, ,
The digital information in Ft, . . . Fn is respectively scanned by scanning line A.
I+ 1 , . . . is displayed on in. The output of the second stage of the shift register section F is supplied to the color converter 177 and is also supplied to the first shift register section F through the gate circuit 8.
n, and its speed is selected so that one circulation period is the same as the surface scanning period of the display 82.

In this state, the contents of the main memory 81 are displayed on the display 82 as a still image. Shift register section F, ~Fn
Each stage represents a digital signal of 4 parallel vias tα
can do. The color converter 177 performs signal conversion to cause the display 82 to emit a predetermined color according to the level of the signal in response to the manually input digital signal, and its output causes the color cathode ray tube display 82 to emit light in a predetermined color. Red, green, and blue electron guns are controlled.

In the transmitting/receiving section 1), a received signal corresponding to one transmission pulse is captured into a data capture memory 34, and the signal in this memory 34 is transferred to the main memory 8L as information on one display line. This new signal is then displayed at a predetermined position on the display.

For example, in the figure, at the beginning of surface scanning, the newest signal is read out from the register section F and displayed on the first scanning line 1). Second line scanning line l! , the data that was in the register Ft at the beginning of surface scanning is read out and displayed. Thereafter, in the same manner, the oldest data present in the register section Fn at the beginning of surface scanning is displayed on the first line scanning line 1). The data acquisition memory 34 has the same capacity as one of the shift register sections F+-Fn of the main memory 81. When writing to the memory 34 is completed, a signal indicating this is supplied to the read pulse generation circuit 9. This circuit 9 includes a control n circuit 7.
to the plane synchronous signal Pν and the line synchronous signal PR shown in FIG. 2C.
is supplied. A read pulse is generated for the t&i synchronization signal period from the next plane sync No. 13 after the above writing is completed, as shown in the second diagram. The read pulses are synchronized with the shift pulses of the main memory 81 and are the same number as the write pulses. The read pulse is sent to the capture memory 3 through the OR circuit 56.
4 is read out, and its output is supplied to the first stage of the soft register Fn through the gate circuit 8. The output of the main memory 81 is also constantly supplied to the shift register 124 for delaying one scanning line. Therefore, when the transfer is completed, the newest data that had been stored in the register section F1 up to that point is in the register section 124, and in this state, the output of the main memory 81 is returned to the first stage shift register section Fn through the shift register 124. The feedback through the delay shift register 124 is a period from the end of reading from the memory 34 until the next surface synchronization signal, as shown in FIG.

Immediately before this surface synchronization signal, the newest data written from the capture memory 34 this time is located in the shift register section F, and the oldest data up to that point is located in the soft register 12.
When the main memory is read from the zero-order plane synchronization signal located at 4, the gate circuit 8 is controlled so that the output of the main memory 81 is fed back to the shift register section Fn. In this way, new data is written to the main memory 81, and the amount of old data is removed from the main memory 81 while remaining in the shift register 124.

In this way, each time data is transferred from the memory 34 to the main memory 81, the newest data is displayed on the line scanning line i, and the oldest data is removed from the main memo IJ 81 and displayed on the display line on the display surface. moves toward the oldest line one by one in the direction perpendicular to that line, and the second newest data is displayed on the line scanning line lz. As a result, an oscillation line 155 corresponding to the oscillation pulse 25, a display 153 corresponding to the seabed 3, and a display 154 corresponding to the school of fish 5 appear on the display surface of the display 82, respectively. In other words, a display similar to the record on the record paper of a conventional fish finder is obtained, and the display moves from right to left in the same way as when the record paper is moved from right to left in FIG. In FIG. 1, if the speed of the received data from the transmitter/receiver 1) and the scanning speed of the cathode ray tube display 82 are appropriately selected, the data acquisition memory 34 is omitted and the data from the AD converter 28 is It is also possible to write directly to main memory 81.

Next, the fish finder according to the present invention will be explained in more detail with reference to the drawings from FIG. 3 onwards. Figures 3 to 5 are divided into parts that should originally be shown as a single drawing, and the symbols in circles attached to the ends of each lead wire indicate that the same wires are connected to each other. ing. In Fig. 3, the transmitting/receiving section 1 is almost the same as that of a conventional fish finder. 1
Changed by selection 4. In other words, the detection range is (1~room, 0~200m, 0~400m, 0~8
The frequency division ratio of the frequency divider 13 is changed depending on the setting, such as 00 m, and the deeper the search is performed, the higher the frequency division ratio becomes, and the frequency of its output becomes lower.

The output frequency-divided in this way is output to the display time switching circuit 15.
For example, one of three frequency division ratios is selected: the standard one, its double, and the standard 2. This circuit is for fish detection using cathode ray tubes, and by selecting the three-point changeover switch 16, when it is in one switching position, the normal display is displayed, and when it is in the other one switching position, the display is normal. A fast-forward display is made, and the output frequency is doubled, and when it is at another switching position 7, a slow-forward display is made, and the output frequency is set to 2 of the normal display. That is, the changeover switch 16 can be used to speed up or slow down the rewriting time of information in the main memory 81 that stores display information for the cathode ray tube display 82, which will be described later.

The output of the display time switching circuit 15 is the repetition period counter 17.
The frequency is further divided by , thereby creating a trigger oscillation period. The output of this repetition period counter 17 is shown, for example, in FIG. 6A, and this output is differentiated by a differentiating circuit 18, and, for example, its rising pulse (FIG. 6B) is extracted. This rising repulse lasts for a period of time equivalent to the propagation time of the ultrasonic pulse at a depth below the water surface to which the transducer 23 is attached, in the stuttering correction circuit 19 consisting of, for example, a monostable multivib break. It is converted into a pulse of time T1 shown in FIG. The converted output is supplied to the transmission trigger generation circuit 21, and a trigger signal delayed by the time TI from the differential pulse (FIG. 6B) is obtained as shown in FIG.

This trigger f drives the transmitter 22, and its output excites the transducer 23, which emits an ultrasonic pulse toward the seabed. Based on the transmission of this ultrasonic pulse, the reflected f The second wave is received by the transducer 23 and then received by the receiver 24, where, for example, as shown in FIG. 4, an oscillation pulse 25, a reflected signal 26 from a school of fish, and a reflected signal 27 from the seabed are received.

The output of the receiver 24 is outputted by an AD converter 28, for example, into four
The data is converted into a bit digital signal and supplied to each of the plurality of data acquisition units.

As a data import unit, a normal display data import unit 31;
If a partially enlarged display data import section 32 and a seafloor enlarged display data import section 33 are provided, the data import memories 34, 35, .
36 are respectively supplied with the outputs of the AD converters on the second day.

In the normal display data acquisition section 31, the gate signal generation circuit 50 is activated by the pulse from the differentiating circuit 18 as shown in FIG.
The shift pulse counter 49 is driven as shown in FIG. 1 to generate a gate signal, and controlled by this gate signal, the shift pulse counter 49 starts a coefficient operation, and the output pulses of the range frequency dividing circuit 13 are counted by the counter 49. The coefficient value of the counter 49 is decoded by a decoder 51, and output terminals of the decoder at appropriate intervals are selected by a shift selection switch 52. The selection fixed terminal of the decoder 51 example of the shift selection switch 52 obtains pulses Ps whose phase is sequentially shifted by 50 m in terms of ultrasonic detection distance, as shown in FIG. 6G, and one of the pulses Ps (Selected by the shift selection I length switch 52, the gate signal generation circuit 53 is driven, and as a result, a gate signal is generated once as shown in FIG. In this state, when the pulse at the second port is increased by il1 by the switch 52, a water depth range between 50 m and 150 m is to be detected.When the shift pulse counter 49 counts a predetermined number and the counter 49 reaches a full count. A time corresponding to at least l shift distance, 100 m in this example, is generated between the time when the next trigger pulse is generated. Sending of the signal is stopped, and as shown in FIG. It is set by the output and reset by the output of the counter 49. The lth gate signal generation circuit is also configured similarly to this gate signal generation circuit 50.

When the output of the gate signal generation circuit 53 becomes a high level, the frequency dividing circuit 54 and the data acquisition counter 55 become operational, and the frequency dividing circuit 54 further divides the frequency of the output of the range frequency dividing circuit 13. The output is counted by a data acquisition counter 55. Further, the output of the frequency dividing circuit 54 is applied to the data acquisition memory 34 through an OR circuit 56, and the output of the AD converter 28 is written into the memory 34 through an OR circuit 57 for each pulse. This counter 5
5 is the number of pixels in one display line on the display 82, for example, 256, which is the full count, and the gate signal generation circuit 53 is controlled by its output, and its output becomes low level. Therefore, the operations of the frequency dividing circuit 54 and the counter 55 are stopped. In other words, the frequency dividing circuit 54 generates a data acquisition pulse as shown in FIG.
Data for each item is imported.

In the partial enlargement display data acquisition section 32, the counter 5
5 is operating, that is, the normal display data acquisition section 3
In order to select and enlarge an arbitrary section while data is being captured in 1, the count contents of the counter 55 are supplied to a decoder 58, and each output of the decoder 5) = 1 is an enlargement position selection switch. 59 selects one 0
For example, the section of the output gate signal of the selection gate signal generation circuit 53 is divided into five equal parts, and pulses whose phases are sequentially shifted corresponding to each of the five parts are sent to the five fixed terminals of the selection switch 59 as shown in FIG. One of the pulses is selected by the switch 59. This selected pulse causes the output of the gate signal generation circuit 61 to go to a high level as shown in FIG. is supplied with the output pulse from the reference oscillator 12,
The frequency division ratio of this frequency dividing circuit 62 is changed by an expansion width selection switch 64, and when the expansion width is increased, that is, the expansion rate is increased, the frequency division ratio is small, so that a high frequency output can be obtained. . This pulse is counted by a data acquisition counter 63 and drives the data acquisition memory 35 through an OR circuit 65, and the output of the AD converter 28 is read into the memory 35 through an OR gate 67.

The counter 63, like the counter 55, reaches a full count at 256 bits, for example, and its full count output controls the gate signal generation circuit 61, its output becomes a low level, and both the frequency dividing circuit 62 and the counter 63 become inactive. . In this way, while the output of the gate signal generation circuit 61 (FIG. 6M) is at a high level, the A of the corresponding received signal is
The D-converted output is read into the memory 35 as 256 sample information, that is, as pixel information of one display line segment.

The differentiation circuit 18 in the mineral display data acquisition section 33
The gate signal generation circuit 68 is driven by the differential pulse shown in FIG. 6, and the frequency dividing circuit 69 is activated by this output signal (L in FIG. 6).
When the reference signal from the oscillator 12 is frequency-divided, and the frequency division ratio is changed according to the expansion rate set by the expansion width selection switch 71, similar to the 0 frequency division circuit 62, when attempting to significantly expand the frequency. The output of the 0 frequency divider 69, which outputs high-speed pulses with a small frequency division ratio, drives the data acquisition memory 36 through the OR circuit 72, and the output of the 0 converter 28 is read for each pulse. . The capacity of this memory 36 is the same as that of the memories 34 and 35, so it becomes full with 256 pulses, but if more data is written than this,
Each time new data is written, the oldest data is sequentially erased.

On the other hand, the output of the receiver 24 is also supplied to the bottom signal detection circuit 73, and a conventionally known circuit can be used for this circuit &S73. A signal larger than the level is detected as a bottom signal. This bottom signal is a pulse as shown in FIG. The data acquisition operation of 36 is also stopped. The latest data captured at this time is the signal reflected from the ocean floor.

Since this kind of data is always imported, the bottom of each l is always at a constant position on the display line, the seabed line is displayed as a straight line, and the upper CD from the seafloor is enlarged and displayed according to the division ratio of RA69. .

The data fetched into the data fetching memories 34, 35, and 36 of the data fetching section as described above is stored in the common buffer memory 79 according to the selection state of the selective reading means 74 to 76 provided correspondingly. Data is imported into. The data taken into this buffer memory 79 is transferred to a main memory 81, and the main memory 81 is repeatedly read out and supplied to a cathode ray tube display 82 to be displayed as an image.

Control of the cathode ray tube display 82 is performed as follows.The output signal from the 0 oscillator 83 is divided by the frequency division circuit 84 to the wA (horizontal) scanning period of the cathode ray tube display 82, and its output is The signal is supplied to a synchronizing signal generating circuit 85, and its output is supplied to a display 82. The output of the frequency divider 84 is also supplied to a plane synchronous U signal generator 86 which divides the frequency to produce a plane synchronous signal, which is supplied to the display 82. Information corresponding to one display line of the display 82 is stored in the buffer memory 79, and information for that one display line is transferred to the king memory 81 as described above.

The data from the data import section is transferred to the buffer memory IJ79 using the clock of the display 82 as a basis.

Therefore, the output of the data acquisition counter 55 and the output pulse of the plane sync signal generation circuit 86 are supplied to the sync selection circuit 87. This plane sync pulse signal is, for example, N in FIG. 6, and the next plane sync pulse after the trailing edge of the full count output of the data acquisition counter 55, that is, the gate signal 61)H, is selected as shown in FIG. 60. Ru.

The gate signal generation circuit 88 is driven four times by this selected plane synchronization pulse, and the sixth rI! A signal as shown in JP is generated, and the frequency divider circuit 89 and data read counter 91 are activated.The line scanning frequency signal from the frequency divider circuit 84 is supplied to the 0 frequency divider circuit 89, The frequency division ratio of the frequency circuit 89 is changed by selecting the display width selection switch 92.

The switch 92 has four fixed terminals, for example a to d, and when connected to a, the frequency division ratio of the frequency divider circuit 89 is 1/8, and when connected to b, the frequency division ratio is set to 1/8. Bal/
4. When connected to C, the frequency division ratio is set to l; when connected to d, it is not connected to the frequency dividing circuit 89 and this selective reading means is not selected. Each negative output of the fixed terminals a to C is supplied to the OR circuit 93, the gate signal generation circuit 88 is cleared by the output, and the output of the circuit 88 is held at a low level. When selected, the selected data is displayed on display 8.
It is displayed as one display line of 2, that is, it is displayed across the entire width of the display, and when terminal C is selected, it is displayed at 1/2 the width, and when terminal C is selected, it is displayed at 1/4 the width. It operates as if

The frequency divided output of the frequency dividing circuit 89 is counted by a read counter 91, and this counter 91 reaches a full count with 256 pulses, similar to the data acquisition counter 55 and the like. As mentioned above, the display width selection switch 92 also serves as a switch for selecting or not selecting the selective reading means.
2 is located at terminal d, this selective reading means is not selected, and the output of the gate signal generating circuit 88 does not go to high level. However, when the selective reading means is selected, the switch 92 is located at terminal a. ”'-c
A frequency divided output is obtained from the frequency dividing circuit 89, and the counter 91 not only counts this output pulse, but also drives the selective reading means 74 and the corresponding data acquisition memory 34 by the pulse. Data is read from this, and the read data is supplied to buffer memory 79 through OR gate 94.

Writing to buffer memory 79 is performed in synchronization with the slowest pulse among the output pulses of frequency divider circuit 89. ! III. The pulse from the frequency divider circuit 84 is sent to the frequency divider circuit 9.
The frequency is divided into 1/8 by 5, and the divided output is sent to the OR circuit 96.
The data from the OR circuit 94 is supplied to the buffer memory 79 through its fJ+ control.
written to. Is this post it+II? The output of the synchronization detection circuit 87 is sent to the gate signal generation circuit 97 in order to
This generates a gate signal as shown in FIG.
5 and the counter 98 are activated, the counter 98 counts the output of the frequency dividing circuit 95, and when it counts a predetermined number, 256 in this example, the gate signal generation circuit 97 is set to Hm by the output, and its output becomes a low level. Become.

The selective reading means 75 and 76 have almost the same configuration as the selective reading means 74, and therefore each gate signal generating circuit 8
8, a frequency dividing circuit 89, a read counter 91, a display width selection switch 92, and an OR circuit 93, which are connected in the same manner. The selection circuits 99 of the 0 selection reading means 75 to 76 each having a selection circuit 99 instead of the synchronization detection circuit 87 are sequentially connected vertically, and the synchronization detection circuit 87 is connected at the preceding stage. Further, the output of the OR circuit 93 is supplied to the next stage selection circuit 99 via the inverter 101, and the output of the counter 91 indicating that reading has ended and the output of the gate signal generation circuit 88 are also supplied to the next stage IK width circuit 99. supplied to

As shown in FIG.
When the output of 01 is at a low level, that is, when the display width selection switch 92 in the previous stage is connected to any of the terminals a to C, the gate 102 is closed, so that the synchronization detection circuit of the selection reading means in the previous stage 87 or the output of the selection circuit 99 cannot pass through the gate 102. However, when the display width selection switch is selected to the terminal d, that is, when the selection reading means is not selected, the output of the inverter 101 of the selection reading means is At a high level,
The gate 102 is opened, and in the case of the selection circuit 99 in the previous stage or the selection reading means 75, the activation signal from the synchronization detection circuit 87 passes through the gate 102 and further passes through the OR gate 103 to become the output of the selection circuit 99.

On the other hand, when the display width selection switch 92 is selected between terminals a to c, the gate 102 is closed as described above, and the gate 104 is opened by the output of the gate signal generation circuit 88 at the previous stage. The final output pulse of read counter 91 is passed through gate 104 and further to OR gate 1.
It is output through 03. In other words, when the selective reading means is not selected, the activation signal from the previous stage is sent as the activation signal to the next stage through the gates 102 and 103, and the display width selection switch 92 is selected to either terminal a''-c. If so, the full count output of the read counter 91 is supplied to the next stage as a start signal.

゛ For example, when the activation signal is given as shown in FIG. 8A, the output of the gate signal generation circuit 88 becomes high level as shown in FIG. 8B, and the selection switch 92 is connected to terminal a. Assuming that the frequency dividing ratio of the frequency dividing circuit 89 is the largest, the reading counter 91 reaches a full count, and the gate signal from the gate signal generating circuit 8 ends as shown in FIG. 8B, the display width selection switch 9
When switch 92 is connected to terminal A, the frequency division ratio of frequency divider circuit 89 is A, so its output frequency is twice that of when switch 92 is connected to terminal a, and therefore the speed is twice as high. The output of the counter 91 becomes a full count, and the output width of the gate signal generation circuit 88 becomes A in FIG. 8B, as shown in FIG. 8C.

Assuming that the switch 92 in the selective readout means 74 is set to terminal C, and the selection switch 92 in the selective readout means 75 is connected to the terminal C, the gate 104 of the selection circuit 99 of the selective readout means 75 is connected to the previous stage readout counter. The full count output of 91 passes and the output of the gate signal generating circuit 88 rises as shown in Figure 8, and since the frequency division ratio of the frequency dividing circuit 89 is set to 2, the selection screening means 74 at this time The counter 91 of the selection IR1 output means 75 reaches a full count at twice the counting speed of the readout counter 91, and the output signal of the gate signal generation circuit 88 becomes low level as shown in FIG. At the end of this signal, when the selection selection means 76 is driven and its display width selection switch 92 is set to terminal C, its gate signal generation circuit 88 similarly generates a signal as shown in FIG. 8E. Output.

As described above, the frequency dividing circuit 95 is selected to have the highest frequency division ratio in the frequency dividing circuit 89, and the full count of the counter 98 is selected to be the same as that of the counter 91, so that the write time to the buffer memory 79 is is the same as the length of the gate signal when the selection switch 92 shown in FIG. 8B is set to the full width terminal a. Therefore, selective reading means? When the display width selection switches 92 of 4, 75, and 76 are set to terminals S, C, and C, respectively, the gate signal generating circuits 88 of the selective reading means 74, 75, and 76 of FIG. The outputs shown in are generated, and during these periods the corresponding data acquisition memory 34,
35 and 36 data are respectively read out and written into the buffer memory 79. The contents of the memory 34 are stored in the buffer memory 79 as shown in FIG.
05, and each content of memory 35, 36 is written as two parts 106, 107, respectively.

In reality, each of the memories 34 to 36.79 has the same capacity, so data is skipped randomly depending on the compression ratio when writing to the buffer memory 79.

The data will be written to the file memory 79.

The display device 82 thus transferred to the buffer memory 79
The information on one display line segment is transferred to the main memory 81. The main memory 81 has a capacity equivalent to one screen of the cathode ray tube display 82. For example, the output of a 0 oscillator 83, which is a not register, is given to the clock generator 1)1, and the main memory 81 is shifted by the clock from this. The output is supplied to the cathode ray tube display 82 and fed back to the main memory 81 through the gate 1)2 and further through the OR gate 1)3. In this example, a 1wa scanning line of the cathode ray tube display 82 is used as one display line, and when the data from the data acquisition section is transferred to the buffer memory 79, the counter 9.8
reaches a full count, and its output (first diagram) is also given to the gate signal generator 1) 4, from which a gate signal is obtained as shown in the 91st page. This signal opens gate 1)5 so that the output of buffer memory 79 can be supplied to main memory 81 through gate 1)5.1)3. Gate signal generation circuit 1) Frequency dividing circuit 1) 6 and counter 1) according to the gate signal from 4
7 is in an operating state, and the output of the oscillator 83 is frequency-divided by the frequency dividing circuit 1) 6 to obtain a clock signal having the same speed as the clock signal of the clock generator 1) 1. This clock signal passes sequentially through gate 301, OR circuits 302 and 96, and is applied as a read clock to buffer memory 79. Therefore, the read clock from buffer memory 79 and the write clock of main memory 81 are synchronized.

When the counter 1) 7 counts pixels for one scanning line, 256 in this example, the count becomes full and the gate signal generation circuit 1) 4 is ill JTJed, its output becomes low level, and the frequency dividing circuit 1 ). 6 and counter 1)7 stop. The output of the counter 98 is also supplied to the gate signal generating circuit 1) 8, and this output becomes a high level as shown in FIG. The signals of the line scanning frequency are counted by this counter 1)9. counter 1
) 9 is a full count when counted by the number of line scanning lines on one screen of the display 82, and the game is
The output of the signal generating circuit 1)8 becomes low level, and the operation of the counter 1)9 also stops. Therefore, gate signal generation circuit 1
) 8 to 9C, a level output is obtained for a length of one screen as shown in FIG. 9C.

A circuit 122 performs an AND operation between this and the output shown in FIG. 9B of the gate signal generating circuit 1) 4, which is inverted by an inverter 121. As a result, the signal shown in FIG. 9 is obtained. It will be done. This signal opens the gate 123,
The output of the main memory 81 is fed back to the main memory 81 through a delay circuit 124 for one scanning line, and further through gates 303, 304, 123, 1)3 in sequence.

In this way, when new information is manually inputted into the main memory 81 from the buffer memory 79, the newest information f[3 in the main memory 81 up to that point is delayed by one scanning line by the delay circuit 124 and the main memory 1) It will be returned to 81. The gate circuit 123 closes one pixel scanning period after the gate circuit 1)5 opens, that is, after information transfer from the buffer memory 79 to the main memory begins.

Therefore, when transferring the information in the buffer memory 79 to the main memory 81, the information on the oldest display line is transferred to the delay circuit 124.
, and will be erased from the main memory 81. Gate signal generation circuit 1 for gate circuit 1) 2
)8 is inverted by the inverter 125, and the signal shown in the 91st line is given.
1) Only 2 is open. Naori lock generator 1) 1
A surface synchronization signal and a line synchronization signal are supplied to the display 82, and generation of a clock signal is stopped in the electron beam retrace section of the display 82.

Next, the various display states of the fish finder described above are shown in the 10th section.
Let us explain its operation with reference to the figure. In Figure 10, the line scanning direction of the display 82 is the vertical direction, and the rightmost position 151 is the display position of the newest ↑ni, and the oldest information is displayed. The display is an example in which the leftmost digit is 1t152. In contrast to the display on the far right of this display screen, the old display for -soba is information from 30 minutes ago.
30 minutes before this, the range switch 14 was set at 800 m.
, and when only 74 is selected as the selection readout means, the seabed display 153, the fish school display 154, and the oscillation line 15 are displayed.
5 appears. The depth scale 156 is 100 in the figure.
It is displayed every m. Further, at the bottom of the display screen, a time scale 157 is displayed as a dot every two minutes, for example.

In the display in Figure 10, 19 minutes before the current time is 0.
Display of detection information for a range of ~800m and 400m of that
This is a case where an enlarged display of a portion of ~500 m is displayed in parallel. The expansion range 400 to 500 is selected by selecting the output of the decoder 58 with the expansion value selection switch 59, and the expansion width, 100 m, is selected by the switch 64. The selection reading means 74 and 75 have a display width of 1! so that the display width 1! is displayed on the upper half and lower half of the display screen, respectively. The selection switch 92 is set to terminal.

In this case, the information from 0 to 800 m is captured as one display line segment into the capture memory 34 as in the previous case, and the information from 400 to 500 m is captured into the memory 35 as one display line. 0 selection reading means 74 taken in as a minute
The contents of the memory 34 are compressed and written to the first half of the buffer memory 79, the right half in the figure,
The contents of the memory 35 are compressed and taken into the latter half. Therefore, as shown in FIG. 10, the seabed is displayed as 161 and the school of fish is displayed as 162, and their enlarged views are further enlarged and displayed as the seabed 163 and the school of fish 164. The depth scale 156 is compressed and displayed as a depth scale 8160.

Further, the output of the gate signal generation circuit 61 indicating the enlarged position is supplied to the enlarged mark generator 170, and the output of the gate signal generation circuit 61 corresponding to the display color (for example, white) is supplied to the enlarged mark generator 170 at the position corresponding to the rising and falling edges of the gate signal of the gate signal generating circuit 61. The resulting digital signal is taken into the data take-in memory 34 through the OR circuit 57. As a result, an enlarged position display line 165 indicating the enlarged position is displayed, indicating that this portion is enlarged downward. Further, the output of the gate signal generation circuit 61 operates the enlarged depth mark generator 166, which divides the output of the frequency divider 13 and generates a depth mark for the enlarged display area. It is written into the enlarged information acquisition memory 35 through the OR circuit 67 as a digital signal indicating the level corresponding to the displayed color. As a result, an enlarged depth mark 167 is displayed on the display.

In addition, in order to provide a boundary line 168 indicating the boundary between the normal display in the upper half and the enlarged display in the lower half, the output of the read counter 91 of the selective reading means 74 is passed through the OR circuit 169, and then passed through the OR circuit 94 to the buffer. The data is written to memory 79. Similarly, when the selective reading means 74 to 77, etc. are selected, the signal indicating the boundary of the display is the output of the reading counter 91 of those selective reading means.
The signal is then supplied to the Banoffer memory 79 as a boundary line signal.

Furthermore, in this example, 1) minutes before the current time, the normal display remains as it is, the enlargement switch 64 is selected to increase the enlargement ratio, the width is enlarged by 50m, the enlargement position selection switch 59 is selected, and the display is displayed between 550m and 600m. This is the case when you select to enlarge the image.

Next, we will explain the most distinctive feature of this invention, where an old image is fixedly displayed in a part of the display screen, and the oldest information is sequentially removed while displaying a new report in the other part. For example, by selecting only the 0 selection readout means 74, the information captured by the normal display data capture unit 31 is displayed completely on the display screen as shown in FIG. Image 154, outgoing line display 1
55 appear respectively. This image is taken when the fishing boat 201 passes through the passage 202 and is at position (2) in FIG. 12, and a school of fish 203 is present on the passage 202. From this state in 1) Figure A, the vertical axis of the image in 1) Figure A is compressed to 1/2 and the lower half of the display screen is The data is displayed in a fixed manner as a fixed display section 204, and the upper half of the screen is displayed as a moving display section 205, in which the oldest data is sequentially removed every time new data is obtained. 1) In Figure B, fishing boat 201 is in passage 2.
This is an image when the moving display section 205 is at the position ■ of 02.
The fish school image moves to the left with respect to the fixed display section 204, that is, to the older side. When fishing FgI 201 reaches position ■, the image of the fish school disappears, and fishing boat 201 appears near the fish school 203 based on the situation of the seabed line.
I understand that it has arrived. The first) figure is that the image on the movable display section 205 almost matches the image on the fixed display section 204, indicating that the fishing boat 201 has come again to almost the same position (■) where the image on the fixed display section 204 was obtained. It will be done. Therefore, fixed display section 2
04 and the fish school 203 while looking at the images on the moving display section 205.
The fishing boat 201 can be reliably brought close to the fishing boat 201.

To display the display shown in Fig. 1), turn off the normal fixed changeover switch 206 shown in Fig. 5, and first change the display of Fig. The contents of the main memory 81 are rewritten so that it is compressed to 1 and displayed in two directions, one above the other. That is, the fixed-movement simultaneous display II control circuit 207 operates, and the terminal IK of the control j'n circuit 207 becomes high level from the end of the surface synchronization signal immediately after the switch 206 is turned off, and this is applied to the game 208. It is also applied to the gate 301 through the inverter 209. Therefore, the read clock when reading information from the buffer memory 79 and supplying it to the main memory 81 is not the output of the frequency divider circuit 1)6 (it is a frequency division ratio that is half the frequency division ratio of this circuit). ,
The clock from the frequency divider circuit 21) which outputs a clock signal twice as fast as the output clock of the frequency divider circuit 1)6 is sent to the gate 20B.
, 302°98 and is applied to the buffer memory 79. Therefore, the buffer memory 79 is read out during the first half of the line scanning period, and the information is stored in the main memory 81 and transferred to the frequency dividing circuit 1.
) 1, that is, the speed of the cathode ray tube display 82.

In FIG. 13, Vs is the 100-scan interval immediately after the fixed changeover switch 206 is turned off, Hs is the line synchronization signal, and VsO is the period immediately after the switch 206 is turned off.
The line scanning period in between is sequentially H+, Ilz, Hi,...
・If we name it, the line scanning period H, ni, J, ? Ia High II m Circuit 207 (from D terminals IF and IG to clock generator 1) A clock α having a speed of 2 of the clock of 1 is connected to the shift register 21 as shown in FIG. 13F and G, respectively.
2 and 213 as shift pulses, respectively.

Therefore, new information from the buffer memory 79 is transferred to the main memory 81.
When writing to the main memory 8I, every other bit of the latest data read from the main memory 8I is stored in the shift registers 212 and 213, respectively. The number of shift stages of each of these shift registers 212 to 215 is selected to be 128, which is half of the number of shift stages of the shift register 124, which is 256.

In the next line scanning period H2, the terminal I of the control circuit 207
From H and II, the clock α is applied to the shift registers 214 and 215 as shown in FIG. Period 14.

In the first half of , a clock β having the same speed as the clock of the clock generator 1) 1 is applied to the terminal IF as shown in FIG. The data in the shift register 212 is transferred to the gates 216, 304, 128.
, 1) 0 period H2 which is returned to the main memory through 3 sequentially.
In the second half of , clock β is sent from terminal IG to shift register 2.
13, and a gate signal shown at 13m8 from terminal IB is also applied to gate 217.
During the 0th line scanning period H1 in which the contents of the shift register 213 are fed back to the main memory 81 through 17, a clock α is generated from the terminals IF and IG, and in the first half, the clock α is generated from the terminal I
A clock β is generated at the terminal IC, a gate signal shown in FIG. 214
．． The data previously stored in 215 is sent to gate 218.21.
9 to the main memory 81. Thereafter, in the same manner, the data for each display line is rewritten in the main memory 81 so that the data is displayed identically in the first half and the second half of the display line. After being rewritten in this way, if new data does not arrive, gates 1) and 2 are opened and the contents of the main memory 81 are displayed as a still image.
) as shown in m8.

From this state, 1) As shown in Figures B, C, and D, the fixed display section 204 displays the previous data in a fixed manner, and the movable display section 205 displays a display that erases old data every time new data is obtained. To do this, use the gate 1) in Figure 5.1)
2,123 as follows, that is, the first
As shown in Figure 5, the surface scanning period Vs when writing new data
, for the line synchronization signal Hs, in the case of normal display, as shown in FIG. 15A, as explained in FIG.
) 2.1) '5, 123 is controlled by the gate signal with the same number, but the display in Figures 1) B, 'C, and D is the 15th-
As shown by the same numbers as the gate signals for gates 1) 2 and 1) 5.123 in 8, gate signals for gates 1) 2 and 1) 5. ) 5, new data appears only in the moving display section 205 in the upper half of the display screen. In the latter half of each line scanning period, the gate 1)2 is opened and the data for the fixed display section 204 in the lower half of the screen is returned to the main memory 8.degree.l without delay, resulting in a still image.

After the second line scanning period, the gate 123 is opened in each first half of the second line scanning period, each of which is delayed by one scanning line, and the display is moved one display line to the right, thereby performing a moving display.

An example of the control circuit 207 is shown in FIG.
6 is applied to the J terminal and its inverted signal terminal of the JK flipflop 7p 231, and this is applied to the gate signal generation circuit 1.
) 8 is read at the trailing edge of the plane sync signal from 8. Therefore, the Q output of the flip-flop 231 becomes high level, the next stage flip-flop 233 becomes active, the output of the gate 234 becomes high level, the flip-flops 235 to 238 become active, and 128 minutes l counter 239 is also activated, and terminal IB goes low, which is applied to gate 303 in FIG. 5, which closes. Line synchronization signal Hs from terminal 241
is divided by 1/2 by a flip-flop 235, and the clock at the terminal 242 is also divided by 2 by a flip-flop 236.
The frequency is divided by 1/1, and this clock is divided into 1/2 by the counter 239.
The frequency is divided into 1/28, and the frequency-divided output is divided into 1/2 by a flip-flop 238. flip flop 2
The AND output of the Q output of 35 and the line synchronization signal Hs is supplied to a flip-flop 237 and divided into two. With these combinations of the output states of the Pflo knobs 235-238, the outputs shown in FIG. 13 are obtained at the terminals IA-IJ.

As mentioned earlier, the display from the state shown in Figure 1) A to the display shown in Figure 1) H is not only used when displaying the same thing in parallel as shown in Figure 1I (■), but also at all times. From this, it is also possible to switch to the display shown in Figure 1) B, C, and D. In this case, another set of normal display data acquisition units 31 shown in FIG. , the data acquisition memory 34 of the normal display data acquisition section through these pre-selection reading means.
The same contents are taken into the first half and the second half of the buffer memory 79, respectively, and transferred from there to the main memory 81, so that the same data can be displayed on the first half and the second half of one display line.

1) From the state shown in Figure A, fix half of the left and right halves of the display screen, for example, the left half, to the
04, and the right half can be used as the moving display section 205. In that case, the fishing boat 201 is located at the positions ■, ■, ■2 in Figure 12.
The images of each person when moving sequentially are shown in Figure 1) E, F, G.
Only the moving display section 205 changes sequentially as shown in FIG.

In this case, the control for gates 1), 5.1) and 2, 123 in FIG. In this case, as explained with reference to FIG. 9, as shown in FIG. 15A, each gate signal for gates 1) 2, 1) 5° 123 is indicated by the same number.

On the other hand, 1) To display figures A, E, F, and G,
As shown in FIG. 15C, in the first half of the surface scanning period, after gate 1) 5 is opened during one line scanning period, gate 123 is opened, and in the second half of the surface scanning period, gate 1) 2 is opened. Since this is a static image display, the left half of the display screen, that is, the older image, is displayed fixedly, and only the right half moves to the left each time new data is entered. The oldest data will be deleted.

1) As shown in Figure ■, the upper half of the screen is the normal display area 31
) and a part of it is displayed as the enlarged display section 312 in the lower half, the upper half is set as the normal display section 31), and the left half of the enlarged display section 312 in the lower half is displayed as the fixed display section. 2
04, and the right half is an enlarged moving display section 313, and the first)
Figures J, K.

In order to display such a display as L, the data from the normal display data import section 31 and the partially enlarged display data import section 32 are selected and read by means 74 and 75.
1) By setting each selection switch 92 to terminal 1, the display shown in FIG. 1 is obtained. From this state, as shown in Figure 15, in the first half of the area scanning period, the right side of the display screen is displayed in a moving manner for both the normal display and the enlarged display, and in the second half of the area scanning period, each line In the first half of the scanning period, the gate 123 is opened to provide a delay of 1 vA scanning period to perform a moving display, and in the second half of each period, the gates 1) and 2 are opened and the output of the main memory 81 is linearly fed back to form a still image.

In the above description, the fixed display and the movable display are each displayed in a concentrated manner on a part of the screen, but they can also be distributed and displayed alternately.

For example, as shown in Figures M and O (1), fixed display is performed on every other display line on the display screen, and on the remaining every other display line, as shown in Figures N and P (1), respectively. To perform a moving display, in order to do this, 1) from the display state of Figure A to the 15th
As shown in FIG. When the line scanning feedback H2°Hs, I(y, . . . Fixed data is displayed on every other scanning line, and moving data is displayed on every other scanning line.Therefore, if new data is not transferred, only data for fixed display is displayed. A switch can be used to switch between displaying the display data and displaying only the moving display data.

In this case, if a color cathode ray tube is used as the cathode ray tube indicator 82, the fixed display and the moving display should be colored in different colors to make them stand out from each other so that the fixed display and the moving display can be easily distinguished. For example, one can be displayed in black and white and the other in color. When using the entire display screen in this way, two main memories are used to always store the same data, and when a fixed display and moving display are used, one is used for fixed display and the other is used for moving display. You can also use it. In the above, a knot register is used as the main memory 81, but a random access memory can also be used. In this case, each address of the memory is associated with each pixel on the display screen, and when new data is input, , it is possible to sequentially read out the necessary data, temporarily store it, write new data in the vacant space, and further move the display by reading out a part, temporarily storing it, and writing it again.

As described above, according to the present invention, past data can be fixedly displayed on a part of the display screen, and current data can be displayed on other parts of the display screen.
By comparing these image displays, it becomes easy to discover and reconfirm the object that caused the reflection.

[Brief explanation of drawings]

FIG. 1 is a block diagram simply showing an example of the ultrasonic detection and display method according to the present invention. J is a waveform diagram for explaining the operation of FIG. 6 is a waveform diagram for explaining the operation of the embodiment shown in FIGS. 3 to 5, FIG. 7 is a diagram showing an example of the selection circuit 99, and FIG. 8 is a diagram showing the operation of the selective read f stage. 9 is a waveform diagram for explaining the operation of the gated jn circuit with respect to the main memory. FIG. 10 is a diagram showing an example of display by the ultrasonic detection display device according to the present invention. ) is a diagram showing various types of fixed display and moving display by the ultrasonic detection display device according to the present invention, 12@ is a diagram showing the relationship between the display in FIG. Waveform diagrams are used to explain the simultaneous moving and fixed display operations in the examples shown in Figs. FIG. 3 is a waveform chart showing gate control in each type. Patent applicant: Koden Seisakusho Co., Ltd. Agent: Takuya Kusano6
Figure Q Piece 70 Four pieces 8 Figure 107 106 1 u Tsuku■Q OLI L (ri r l-1ya 1) area (I B c
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Total 1-1 “-1-” “-shi-”-11111 [1) 2co-m-≧F publication flJ]”-1 Procedural Amendment Item 1, Indication of Case Patent Application 1986- 2487852, Title of invention Ultrasonic detection and display method 3, Person performing correction
Relationship to the case Patent applicant 1) 7 Koden Seisakusho Co., Ltd. 4, Agent 2-21 Shinjuku 4-chome, Shinjuku-ku, Tokyo
No. Sagami Building (03-350-6456) 5, Subject of amendment Specific Cattle Claims column Patent Claims

Claims (1)

[Claims] (1) The main memory is repeatedly read out in synchronization with the scanning of the display surface of the scanning display, and the main memory is capable of storing display information for one display screen of the scanning display, and the main memory is repeatedly read out in synchronization with the scanning of the display surface of the scanning display. The detected information is supplied to the scanning display as display information, and the detection information consisting of the reflected waves of the emitted ultrasonic pulses is converted into a digital signal, and the digital signal is temporarily written to a buffer memory. The amount of writing is the same as the number of pixels on one line scanning of the scanning type display, and after the writing is completed, the data is transferred to the main memory during the area scanning period of the scanning type display, and thereby the new detection is performed. Ultrasonic detection in which information forms one display line on a predetermined line scanning line on the display surface of a scanning display, and the screen is moved by sequentially moving other display lines toward the oldest. In the display method, the information read from the main memory while displaying the one detection information as a display line of one line scanning line is synchronized with the line scanning,
The first or second read speed is half the main memory read speed.
The second or first memory is written to the main memory at the same speed in synchronization with the reading of the main memory, and the image that has been displayed up to that point is displayed on the display screen in the direction of the display line. The compressed images are compressed to one half, the same two compressed images are arranged and displayed in the display line direction, and then the digital signals from the buffer memory are read out at twice the writing speed to the main memory. An ultrasonic detection and display method characterized by transferring the new detection information to the main memory and displaying new detection information only on one of the two images on the display screen and moving the screen.