JPS582628B2 - Video display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an image display device that displays detection information from a fish finder on a cathode ray tube display device, and in particular, selection of the display range, partial enlargement, or selection of various modes such as parallel display. The present invention relates to an image display device configured to do so.

Conventionally, for example, in a fish finder, detection information has been recorded on recording paper as grayscale information.

However, the resolution of the grayscale information was poor, making it impossible to judge the information in detail.

From this point of view, it has been proposed to display detected information on a cathode ray tube in the same format as recorded on recording paper, thereby increasing the resolution of the information.

In particular, by using a color cathode ray tube as a cathode ray tube and displaying different colors depending on the level of detected information, resolution can be further improved by displaying not only changes in shading but also changes in color. For example, detection information with small level differences, such as schools of fish in plankton, can be distinguished.

By using a cathode ray tube display in this way, the performance of the fish finder can be significantly improved.

When performing cathode ray tube display in this way, the present invention can, for example, select the detection width, that is, range selection of how many meters deep from On to display, or divide the detection information into equal parts and display only one of them. Selective shift selection for selective display, enlargement display for enlarging a part of these displays, bottom enlargement display for enlarging only the vicinity of the water bottom, and furthermore, for example, on a trawler, the part of the fishing net is called a net height meter. , an ultrasonic detector is installed to detect information above and below the fishing net, and various display modes are selected, such as displaying this information in parallel with fishing information from a fish finder attached to the fishing boat pulling the fishing net. The present invention provides an image display device provided with means.

In this invention, a cathode ray tube display device, particularly a color cathode ray tube display device, is provided, and display information is supplied to the display device from a main memory that stores display information for one screen of the display. The requested still image is displayed.

Of course, this cathode ray tube display is provided with vertical and horizontal deflection means.

Furthermore, in order to provide a color display, a color matrix circuit is provided which performs an operation of displaying display signals supplied from the main memory to the display in different colors depending on their levels.

This matrix circuit generates signals that control the three primary color electron guns of the color cathode ray tube depending on the level of input information.

On the other hand, the detection information from the fish finder is converted into a digital signal, and the converted signal is written into the main memory as information on one display line of the cathode ray tube display.

In this case, there is generally a large difference between the speed at which information can be obtained based on one oscillation pulse from the fish finder and the speed at which the signal is supplied to the fishfinder, so the received information converted into a digital signal is After entering the acquisition memory, it is transferred to the main memory via a buffer memory.

The data is captured into the data capture memory as information on one display line.

For example, if you want to import detection information in a range of 1000m from Om, or if you want to import detection information in a range of 1500m from Om, then 100m and 100m from Om in one detection information.
10, such as 200m from 200m and 300m from 200m.
When dividing data into 0m segments and importing one of them, or when enlarging a part and importing it as a single display line segment, in addition to importing data in this way, it is also possible to especially select only parts such as the ocean floor. In various cases, such as when enlarging and capturing as a single display line, a pulse with a phase indicating the time position of the captured data is obtained using the transmitted ultrasonic wave as a reference, and from that pulse position, the target enlargement rate or compression rate is adjusted. A fixed number of pulses are generated at corresponding speeds, that is, the number of pixels of one display line on the display screen, and the digitally converted detection information is respectively taken into the corresponding data acquisition memory.

Furthermore, other data, such as the information from the above-mentioned net height meter, is synchronized with the signal from the fish finder, and the digital information is converted to digital information and is imported into the data acquisition unit as information for one display line. .

As described above, a plurality of data import units are provided, and the data imported into these units is written into the buffer memory according to the selection and settings of the corresponding selective reading means.

Each of the selective reading means has a selection circuit, and these selection circuits are connected in cascade, and when this selection circuit is selected, the reading clock generation circuit of the selective reading means operates and reads a predetermined number of times after receiving the activation signal. A clock is generated, and in response to this clock signal, the corresponding data acquisition memory is read and the buffer memory is written.

When the writing is completed, an activation signal is supplied to the next stage selection circuit.

When the selection circuit is not selected, the received activation signal is passed to the next stage selection circuit.

Each selection readout means is provided with means for setting the clock frequency of its readout clock generation circuit, and the selected data is displayed on one display line according to the setting.
It is determined whether the main length, half length, or quarter length is displayed.

On the other hand, the writing speed of the buffer memory is set to a constant value that is approximately equal to the slowest reading clock set by the setting means.

Therefore, if the data acquisition memory is read quickly, the information is written to the buffer memory as compressed information.

In addition, in the case of fast reading in this way, data acquisition memory information corresponding to the next selected selective reading means can be written into the buffer memory, and a plurality of data corresponding to one display line can be written into the buffer memory. Information from acquisition memory is written in a compressed form.

In this way, various modes can be displayed in parallel.

If one item is selected, that data is displayed as one display line.

Next, an image display device according to the present invention will be explained with reference to the drawings.

In the figure, numeral 11 is a transmitting and receiving part of the fish finder, which is similar to that of a conventional fish finder.

That is, the reference signal from the reference oscillator 12 is sent to the range frequency divider 1.
3, and the frequency division ratio is changed by selecting the range switch 14.

In other words, the detection range is, for example, 0-100m, 0-200m,
The frequency division ratio of the frequency divider 13 is changed depending on whether the distance is 0 to 400 m, 0 to 800 m, etc., and the deeper the search is performed, the higher the frequency division ratio is and the lower the output frequency is.

The output frequency-divided in this way is output to the display time switching circuit 15.
For example, one of three frequency division ratios is selected: the standard one, its double, and 1/2 of the standard.

This circuit is unique to the image display device using this cathode ray tube, and is selected by selecting the three-point selector switch 16.
When it is in one switching position, the normal display is displayed, when it is in the other switching position, it is a fast forward display and the output frequency is doubled, and when it is in another switching position, it is a slow display and the output frequency is is 1/2 of the normal display.

That is, the changeover switch 16 is used to speed up or slow down the rewriting time of information in the main memory that stores display information for a cathode ray tube display, which will be described later.

The output of the display time switching circuit 15 is the repetition period counter 17.
The frequency is further divided by , thereby creating a trigger oscillation period.

The output of this repetition period counter 17 is shown, for example, in FIG. 4A, and this output is differentiated by a differentiating circuit 18, and, for example, its rising pulse (FIG. 4B) is extracted.

This start-up repulse is generated by the hoarseness correction circuit 19 for the propagation time of the ultrasonic pulse at a depth below the water surface where the hoarseness transducer is attached, for example, by a monostable multi-vibration break.
It is converted into a pulse of time T1 shown in FIG. 4C.

The converted output is supplied to the transmission trigger generation circuit 21,
As shown in FIG. 4D, a trigger signal delayed by time T1 from the differential pulse (FIG. 4B) is obtained.

This trigger signal drives the transmitter 22, and its output excites the transducer 23, so that ultrasonic pulses are emitted toward the seabed.

Based on the transmission of this ultrasonic pulse, its reflected signal is received by the transducer 23 and received by the receiver 24. For example, as shown in FIG. 26, a seabed reflection signal 27 is received.

The output of the receiver 24 is outputted by an AD converter 28, for example, into four
The data is converted into a bit digital signal and supplied to each of the plurality of data acquisition units.

As a data import unit, a normal display data import unit 31;
In the case where a partial enlarged display data import section 32 and a seafloor enlarged display data import section 33 are provided, the data import memories 34, 35 of these data import sections 31, 32, 33,
36 are supplied with the outputs of the AD converters 28, respectively.

In this embodiment, the above-mentioned net height meter information can also be displayed, and as shown in FIG. 5, a fish finder transducer 23 is attached to the bottom of a fishing boat 37.
As a result, ultrasonic waves are transmitted and received as described above.

At the same time, a fishing net 39 is pulled by the rope 38, and a net height meter 41 is attached to the upper part of the fishing net near the opening.

Ultrasonic waves are transmitted to the upper and lower sides of this net height meter 41, and the reflected waves are received.The received signal is received by the receiver 42 of the fishing boat 37 using the ultrasonic wave as a carrier wave. Ru.

That is, in FIGS. 1 to 3, the transducer 43 is the net height meter 41.
The signals from the receiver 42 are received by the receiver 42 .

The upper detection signal part and the lower detection signal part in the received signal are separated by data acquisition sections 44 and 45, respectively.

For the data acquisition memories 46 and 47 for these,
A received signal from the receiver 42 is converted into a digital signal by an AD converter 48 and supplied to each digital signal.

In the normal display data acquisition section 31, the gate signal generation circuit 50 is activated by the pulse from the differentiating circuit 18 as shown in FIG.
The shift pulse counter 49 is driven as shown in FIG. 1 to generate a gate signal, and controlled by this gate signal, the shift pulse counter 49 starts a counting operation, and the output pulses of the range frequency dividing circuit 13 are counted.

The count value of the counter 49 is decoded by a decoder 51, and output terminals of the decoder at appropriate intervals are selected by a shift selection switch 52.

The selection fixed terminal on the decoder 51 side of the shift selection switch 52 selects, for example, pulses PS whose phase is sequentially shifted by 50 m in terms of ultrasonic detection distance, as shown in FIG. is selected by the shift selection switch 52, the gate signal generation circuit 53 is driven, and a gate signal is generated as shown in FIG. 4H.

In this figure, the second pulse is selected by switch 52 to detect a water depth range between 50 m and 150 m.

The shift pulse counter 49 is configured to count a predetermined number and reach a full count with an interval corresponding to at least one shift distance, in this example 100 m, before the next trigger pulse is fired. .

By this full count output, gate signal generation circuit 50
is turned off, its output becomes low level as shown in FIG. 4F, and the counting operation of the counter 49 is stopped.

When the output of the gate signal generation circuit 53 becomes high level, the frequency divider circuit 54 and the data acquisition counter 55 become operational, and the frequency divider circuit 54 further divides the frequency of the range frequency divider circuit 13. The output is counted by a data acquisition counter 55.

Further, the output of the frequency dividing circuit 54 is applied to the data acquisition memory 34 through an OR circuit 56, and the output of the AD converter 28 is written into the memory 34 through an OR circuit 57 for each pulse.

This count 55 is the prime number of one display line, for example 25
6, the full count is reached, and the gate signal generation circuit 53 is controlled by its output, and its output becomes low level.

Therefore, the operations of the frequency dividing circuit 54 and the counter 55 are stopped.

That is, a data acquisition pulse as shown in FIG. 4 is generated from the frequency dividing circuit 54, and the data acquisition memory 34 is, for example, a shift register, and data corresponding to 256 of the data acquisition pulse is acquired.

In the partial enlargement display data acquisition section 32, the counter 5
5 is operating, that is, the normal display data acquisition section 31
In order to select and enlarge an arbitrary section while data is being taken in, the count contents of the counter 55 are supplied to a decoder 58, and one output terminal of the decoder 58 is selected by an enlargement position selection switch 59. Ru.

For example, the section of the output gate signal of the selection gate signal generation circuit 53 is divided into five equal parts, and pulses whose phases are sequentially shifted corresponding to each of the five parts are sent to the five fixed terminals of the selection switch 59 as shown in FIG. One of the pulses is selected by the switch 59.

This selected pulse causes the output of the gate signal generation circuit 61 to go to a high level as shown in FIG.

The output pulse from the reference oscillator 12 is supplied to the frequency dividing circuit 62, and the frequency division ratio of this frequency dividing circuit 62 is changed by the expansion width selection switch 64. The frequency division ratio is small so that a high frequency output can be obtained.

This pulse is counted by the data acquisition counter 63 and the data acquisition memory 35 is driven by 1 through the OR circuit 65, and the output of the AD converter 28 is read into the memory 35 through the OR gate 67.

The counter 63, like the count 55, reaches a full count at 256 bits, for example, and its full count output controls the gate signal generation circuit 61, its output becomes low level, and both the frequency divider circuit 62 and the count 63 become inactive. .

In this way, while the output of the gate signal generation circuit 61 (K in FIG. 4) is at a high level, the AD-converted output of the corresponding received signal is generated as 256 sample information, that is, the pixels of one display line. The information is read into the memory 35 as information.

In the bottom enlarged display data acquisition section 33, the differentiation circuit 18
The gate signal generation circuit 68 is driven by 1 by the differential pulse shown in FIG. 4B, and this output signal (FIG. 4L)
The frequency divider circuit 69 is put into operation.

The frequency dividing circuit 69 divides the frequency of the reference signal from the oscillator 12, and the frequency division ratio is changed according to the expansion rate set by the expansion width selection switch 71.

Similar to the frequency divider circuit 62, when the frequency is to be significantly expanded, high-speed pulses with a small frequency division ratio are output.

The output of the frequency dividing circuit 69 drives the data acquisition memory 36 through the OR circuit 72, and the output of the AD converter 28 is read every pulse.

The capacity of this memory 36 is the same as that of the memories 34 and 35, so it becomes full with 256 pulses, but if more data is written than this, each time new data is written, the most fortune-telling data is sequentially written. It disappears into.

First, the output of the receiver 24 is also supplied to a base detection circuit 73, and a conventionally known circuit can be used as this circuit 73. For example, from the transmission output of an oscillation pulse to the transmission of the next oscillation pulse, A high signal at or above a predetermined level is detected as a bottom signal.

This bottom signal is a pulse as shown in FIG. Data acquisition operations are also stopped.

The latest data captured at this time is the signal reflected from the ocean floor.

Since such data is always captured, the seabed is always at a constant value on the display line, the seafloor line is displayed as a straight line, and the portion above the seafloor is enlarged and displayed according to the frequency division ratio of the frequency divider 69.

The data acquisition operations of the data acquisition units 44 and 45 for the net height meter will be described later for convenience of explanation, but as described above, the data acquisition memories 34 and 45 of the data acquisition units
The data taken into the memory 35, 36, 46, and 47 is taken into a common buffer memory 79 according to the selection state of the selective reading means 74 to 78 provided correspondingly thereto.

The data taken into this buffer memory 79 is transferred to a main memory 81, and the main memory 81 is repeatedly read out and supplied to a cathode ray tube display 82 to be displayed as an image.

Control of the cathode ray tube display 82 is performed as follows.

The output signal from the oscillator 83 is frequency-divided by a frequency dividing circuit 84 to the line (horizontal) scanning period of the cathode ray tube display 82, and its output is supplied to a line synchronization signal generation circuit 85, which outputs the signal to the display 82. Supplied.

The output of the frequency divider 84 is also supplied to a plane (vertical) sync signal generator 86, which divides the frequency to produce a plane sync signal.
This is supplied to the display 82.

Information corresponding to one display line of the display 82 is stored in the buffer memory 79, and information for that one display line is transferred to the main memory 81 as described above.

The data from the data acquisition section is transferred to the buffer memory 79 using the clock on the display 82 as a reference.

Therefore, the output of the data acquisition counter 55 and the output pulse of the synchronization signal generation circuit 86 are supplied to the synchronization detection circuit 87.

This plane synchronous pulse signal is, for example, N in FIG. 4, and is the full count output of the data acquisition counter 55, that is, H in FIG.
The next plane sync pulse at the trailing edge of the gate signal is selected as shown in FIG.

The gate signal generation circuit 88 is driven by the selected plane synchronization pulse, and the circuit 88 generates a signal as shown in FIG.

A line synchronization signal from the frequency dividing circuit 84 is supplied to the frequency dividing circuit 89, and the frequency division ratio of the frequency dividing circuit 89 is changed by selection of the display width selection switch 92.

There are four fixed terminals of this switch 92, for example, a to d. When connected to a, the frequency division ratio of the frequency divider circuit 89 is set to 1/8, and when connected to b, the frequency division ratio is set to 1/8. is 1/4
, C, the frequency division ratio is set to 1. When connected to d, the frequency division ratio is set to 1. If connected to d, the frequency division ratio is not connected to the frequency division circuit 89, and this selection reading means 74 is not selected.

Each negative output of the fixed terminals a to c is supplied to the OR circuit 93, and the gate signal generation circuit 88 is cleared by the output, and the output of the circuit 88 is held at a low level.

When terminal a is selected with the display width selection switch 92, the selected data is displayed as one display line on the display, that is, it is displayed across the entire width of the display, and when terminal b is selected, the selected data is displayed as one display line on the display, and when terminal b is selected, the selected data is displayed as one display line on the display. If terminal C is selected, the screen will be displayed at 1/4 of the width.

The frequency divided output of the frequency dividing circuit 89 is counted by a read counter 91, and this counter 91 reaches a full count with 256 pulses, similar to the data acquisition counter 55 and the like.

As mentioned above, the display width selection switch 92 also serves as a switch for selecting or invoking the selective reading means 74, and when the switch 92 is located at the terminal d, this selective reading means is not selected. , the output of the gate signal generation circuit 88 does not go to high level.

However, when the selective readout means 74 is selected, the switch 92 is connected to any of the terminals a to c, and a frequency divided output is obtained from the frequency dividing circuit 89, and this output pulse is only counted by the counter 91. First, the data fetching memory 34 corresponding to the selective reading means 74 is driven, one disk is read out from the memory 34, and the read data is supplied to the buffer memory 79 through the OR gate 94.

Writing to buffer memory 79 is performed in synchronization with the slowest pulse among the output pulses of frequency divider circuit 89.

That is, the pulse from the frequency dividing circuit 84 is divided into 1/2 by the frequency dividing circuit 95.
The divided output is supplied to the buffer memory 79 through the OR circuit 96, and the data from the OR circuit 94 is written into the buffer memory 79 under the control of the OR circuit 96.

In order to control this writing, the output of the synchronization detection circuit 87 is also supplied to the gate signal generation circuit 97.
A gate signal is generated as shown in FIG.
When the predetermined number is counted, 256 in this example, the gate signal generation circuit 97 is controlled by the output, and the output becomes low level.

The selection readout means 75, 76, 77, and 78 have the same configuration as the selection readout means 74, and correspond to a gate signal generation circuit 88, a frequency division circuit 89, a readout counter 91, a display width selection switch 92, and an OR circuit 93, respectively. The same numbers are shown with suffixes a, b, c, and d, respectively.

Instead of the synchronization detection circuit 87, a selection circuit 99at99b,
99C and 99d are provided, respectively.

Each selection circuit 99a to 99b of the selection reading means 75 to 78
are sequentially connected in cascade, and a synchronization detection circuit 87 is provided at the previous stage.
is connected.

Also, the outputs of the OR circuits 93, 93a, 93b+93c are outputted to inverters 101, 101a, 101b, 10, respectively.
1c to the next stage selection circuits 99a, 99b, 99c,
99d, and the outputs of counters 9L91a, 9lb, 91c indicating that reading has ended and the outputs of gate signal generation circuits 8B, 88a, ssb, 88c are also supplied to the next stage selection circuits 99a, 99b, 99c, 9, respectively.
9d.

As shown in FIG. 6, the selection circuit 99a selects the output of the inverter 101 when the output of the inverter 101 at the previous stage is at a low level, that is, when the display width selection switch 92 at the previous stage is connected to any of the terminals a to C. Since the output is at a low level and the gate 102 is closed, the output of the synchronization detection circuit 87 (or selection circuit 99) of the preceding stage selective reading means cannot pass through the gate 102.

However, when the display width selection switch is selected to terminal d,
That is, when the selective reading means is not selected, the output of the inverter 101 of the selective reading means becomes high level, the gate 102 is opened, and the previous stage selection circuit 99a,
(99b, 99c) or in the case of 1,000 stages of selective reading 75, the activation signal from the synchronization detection circuit 87 passes through the gate 102 and further passes through the OR gate 103 to become the output of the selection circuit 99a.

On the other hand, when the display width selection switch 92 selects one of the terminals a to C, the gate 102 is closed as described above, and the gate 104 is opened by the output of the gate signal generation circuit 88 at the previous stage.

The final output pulse of read counter 91 is gated 104.
The signal is further outputted through the OR gate 103.

In other words, when the selective reading means is not selected, the activation signal from the previous stage is sent as the activation signal to the next stage through the gates 102 and 103, and the display width selection switch 92 is selected to any one of the terminals a to c. In this case, the full count output of the read counter 91 is supplied to the next stage as a start signal.

Selection circuits 99b to 99d are similarly configured.

For example, when the activation signal is given as shown in FIG. 7A, the output of the gate signal generation circuit 88 becomes high level as shown in FIG. 7B, and the selection switch 92 is connected to terminal a. Assuming that the frequency dividing ratio of the frequency dividing circuit 89 is large, the reading counter 91 reaches a full count, and the gate signal from the gate signal generating circuit 88 ends as shown in FIG. When the switch 92 is connected to the terminal a, the frequency division ratio of the frequency divider circuit 89 becomes 1/4, so the output frequency is twice as high as when the switch 92 is connected to the terminal a. The output of the gate signal generating circuit 88 becomes a full count, and the output width of the gate signal generating circuit 88 becomes % of that of FIG. 7B, as shown in FIG. 7C.

Assuming that the switch 92 in the selective readout means 74 is set to terminal b, and the selection switch 92a in the selective readout means 75 is connected to terminal C, the gate 104 of the selection circuit 99a of the selective readout means 75 is connected to the previous stage readout counter. When the full count output of 91 passes through, the output of the gate signal generating circuit 88a rises as shown in FIG. The count 91 reaches a full count at twice the counting speed of the readout counter 91 of the selective readout means 74, and the output signal of the gate signal generation circuit 88a becomes low level as shown in FIG. 7D.

When the selection reading means 76 is driven at the end of this signal and its display width selection switch 92b is set to terminal C, its gate signal generation circuit 88b similarly outputs a signal as shown in FIG. 7E. do.

As mentioned above, the frequency divider circuit 95 is selected to be the same as when the frequency division ratio in the frequency divider circuit 89 is the highest, and the full count of the count 98 is selected to be the same as that of the count 91, so writing to the buffer memory 79 is not possible. The time is the same as the length of the gate signal when the selection switch 92 shown in FIG. 1B is set to the full width terminal a.

Therefore, when the display width selection switches 92, 92a, 92b of the selective reading means 74, 75, 76 are set to the terminals b, c, respectively, the gate signal generating circuits 8B, 88a, The outputs shown in FIG. 7C, D, and E are generated from 88b, and during these periods, all the data in the corresponding data acquisition memories 34, 35, and 36 are read out and written into the buffer memory 79.

The contents of the memory 34 are written into the buffer memory 79 as 105 in 1/2 of the buffer memory 79 as shown in FIG. 7F.
Each content of memories 35 and 36 is 1/4 part 10
6,107.

In reality, each of the memories 34 to 36 and 79 has the same capacity, so data is written to the buffer memory 79 with data being skipped intermittently depending on the compression ratio when writing to the buffer memory 79.

Display device 8 transferred to buffer memory 79 in this way
Information on one display line segment of 2 is transferred to the main memory 81.

The main memory 81 is, for example, a shift register having a capacity for one screen of the cathode ray tube display 82.

The output of oscillator 83 is given to clock generator 111,
The main memory 81 is shifted by the clock from this,
The output is supplied to the cathode ray tube display 82, and is also sent to the main memory 81 through a gate 112 and an OR gate 113.
will be returned to.

In this example, one scanning line of the cathode ray tube display 82 is used as one display line, and when the data from the data acquisition unit is transferred to the buffer memory 79, the counter 98
reaches a full count, and its output (FIG. 8A) is also given to the gate signal generator 114, from which a gate signal as shown in FIG. 8B is obtained.

This signal opens gate 115 so that the output of buffer memory 79 can be supplied to main memory 81 through gates 115 and 113.

The gate signal from the gate signal generation circuit 114 puts the frequency dividing circuit 116 and the counter 117 into operation, and the frequency dividing circuit 116 divides the output of the oscillator 83 to generate a clock signal having the same speed as the clock signal from the clock generator 111. is obtained.

This clock signal is applied as a read clock to buffer memory 79 through OR circuit 96.

Therefore, the read clock from buffer memory 79 and the write clock of main memory 81 are synchronized.

When the counter 117 counts pixels for one scanning line, 256 in this example, the count becomes full and the gate signal generation circuit 114 is controlled, its output becomes low level, and the frequency divider circuit 116 and counter 117 operate. stops.

The output of the counter 98 is also supplied to the gate signal generation circuit 118, and this output becomes a high level as shown in FIG. signals are counted by this counter 119.

When the counter 119 counts the number of line scanning lines on the negative screen of the display 82, it reaches a full count, and its output causes the output of the gate signal generation circuit 118 to go to a low level, and the operation of the counter 119 also stops.

Therefore, a high level output having a length of one screen as shown in FIG. 8C is obtained from the gate signal generating circuit 118.

A circuit 122 performs an AND operation between this and the output shown in FIG. 8B of the gate signal generation circuit 114 inverted by the inverter 121, thereby obtaining the signal shown in FIG. 8D.

The gate 123 is opened by this signal, and the main memory 81
The output is fed back to the main memory 81 through the delay circuit 124 for the negative scanning line, and further through the gates 123 and 113.

In this way, when new information is input from the buffer memory 79 to the main memory 81, the most recent information in the main memory 81 up to that point is returned to the main memory 81 with a delay of one scanning line by the delay circuit 124. Become.

The gate circuit 123 closes one stroke scanning period after the gate circuit 115 opens, that is, after the transfer of information from the buffer memory 79 to the main memory begins.

Therefore, when transferring the information in the buffer memory 79 to the main memory 81, the information on the oldest display is transferred to the delay circuit 124.
, and will be erased from the main memory 81.

For the gate circuit 112, a gate signal generation circuit 118
A signal shown in FIG. 8E, which is obtained by inverting the output of .

This example is for color display as mentioned above, and the output of the main memory 81 is sent to the color matrix circuit 12.
7.

The color matrix circuit 127 outputs a color signal according to the level of digital information input thereto, and has an amplitude (intensity) of 1 to control the electron gun that controls the red color of the display 82. Terminal R1, terminal R2 with amplitude 2,
Furthermore, it has a terminal G1 with an amplitude of 1 and a terminal G2 with an amplitude of 2, which control the color of green, and a terminal B1 with an amplitude of 1 and a terminal B2 with an amplitude of 2, which control the blue color, depending on the digital information input from the main memory 81. Then, any one or two of these six terminals
output occurs.

In order to further increase the variety of colors, even in the case of the same color, control is performed for bright and dark cases.

That is, the least significant bit of the input digital information is displayed on the display 8.
It is supplied to the brightness control terminal of No. 2.

A strong level of reflected signal, such as from the seabed, is displayed in red, a state of no reflection is displayed in blue, and a relatively low level reflected signal, such as from a school of fish, is displayed in yellow, making it relatively conspicuous. The relationship between the human digital information level and the color signal output is selected as follows.

Next, we will discuss how to import data from the net height meter.

Regarding the net height meter, as described in Figure 5, the seine net 39
Detection of the upper and lower sides of the net height meter 41 is performed in a time-division manner near the opening of the net height meter 41.

For example, as shown in FIG. 9, the upper detection section TU and the lower detection section Tl appear alternately, and the force of the lower detection section Tl is selected to be long so that these sections can be distinguished.

The information from this net height meter is given as a negative pulse by the pulses PSU and Psl indicating the transmission trigger, and in response to this, the reflected signal 128 from a school of fish and the reflected signal 1 from the seabed.
29 etc. is given as a positive pulse.

The G side synchronization pulse PSU is detected by the G side synchronization detection circuit 130 in FIG.

Since the detection distance of the net height meter is relatively short, each transmission trigger period is also short, so if you import data for this net height meter after the data acquisition for the fish finder side has been completed, the data for this meter will be There is a possibility that the contents of the data acquisition memory for the net height meter may be rewritten in the middle before the acquisition is performed in the main memory 81.

Therefore, when the data is transferred to the buffer memory 79 and an output from the counter 98 indicating that the process is completed is obtained, the immediately following synchronization pulses PsU and Psl are detected and the subsequent data are respectively taken into the data acquisition memories 46 and 47.

That is, in the upper data acquisition section 44, the synchronization detection circuit 1
32 detects the upper synchronizing pulse PSU immediately after the output pulse of the counter 98, and the output of the gate signal generating circuit 133 is set to a high level.

The frequency divider circuit 134 and counter 135 are put into operation by the output.

The frequency division circuit 134 has its frequency division ratio changed by the write width setting switch 136, divides the frequency of the signal from the oscillator 12, and supplies the divided signal to the counter 135.

The counter 135 counts the number of pixels for one display line, which is 256, and uses the output to generate the gate signal generator 13.
3 is controlled to a low level, and the operations of the frequency dividing circuit 134 and the counter 135 are stopped.

The output of the frequency divider circuit 134 is supplied to an up-down count 137 and up-counted, and the output of an AD converter 48 that digitally converts the output of the receiver 42 to the net height meter using the contents of the up-down count 13γ as an address. is written to data acquisition memory 46.

This data acquisition memory 46 is a random access memory.

When data is to be retrieved from this memory 46, that is, when the selective reading stage 77 is selected, the output of the frequency dividing circuit 89c is counted down by the up-down counter 135, and the output of the memory 46 is read out according to the contents. .

In other words, the newest data among the data written in this manner is read out, that is, the order of the data is reversed.

This is because the detection signal for the upper side of the net height meter is a reflected signal from something closer to the sea surface as the received information is slower than the oscillation trip force, so the display is made to match this.

Similarly, for the lower detection data acquisition stage 45 of the net height meter, information following the upper synchronization pulse PSU is stored in the memory 46.
The synchronization detection circuit 138 detects the lower synchronization pulse Psl immediately after the upper synchronization pulse PSU when written to the synchronous detection circuit 138, and uses its output to set the output of the gate signal generation circuit 139 to a high level and control the frequency division circuit 141 and counter 142. The frequency dividing circuit 141 divides the frequency of the signal from the oscillator 12 and supplies it to the counter 149.

The frequency division ratio can be changed by setting the switch 143,
Further, the frequency-divided output drives the data acquisition memory 47 through the OR circuit 144, and the output of the AD converter 48 is written therein.

In this way, the detection information on the lower side is written to the memory 47, and when the counter 142 counts the number of pixels for one display line, it reaches a full count and controls the gate signal generation circuit 139.
The output is set to a low level and the operation is stopped.

The data in this data acquisition memory 47 is read out by selective reading means 78.

Next, the operation will be explained with reference to diagrams showing various display states using the above-described image display device.

FIG. 10 shows an example of the display screen of the display 82.

In the figure, the line scanning direction of the display 82 is the vertical direction, and the rightmost position 151 is the display position of the newest information, and the oldest information is displayed at the leftmost position 15.
This is an example in which the number is displayed as 2.

In contrast to the display on the far right of this display screen, the oldest display on the left is information from 30 minutes ago, and 30 minutes ago, the range switch 14 was set to 800 m, and the selection readout means was only 74. When selected, a seabed display 153, a display 154 of weak reflected signals from schools of fish, etc., and an oscillation line 155 appear.

Depth scales 156 are displayed every 100 m in the figure.

Furthermore, a time scale 157 is displayed at the bottom of the display screen.

To provide a depth scale 156, the output of frequency divider circuit 13 in FIG. 1 is applied to a depth scale generator 158.

The depth scale generator 1 is activated by the output of the gate signal generation circuit 50.
58 is activated, the output of the frequency dividing circuit 13 is divided, the entire display width of the display 82, that is, one display line is divided into eight equal parts in this example, and a pulse corresponding to each division position is generated. , each pulse is sent to the OR circuit 5 as a numerical value indicating a predetermined level, for example, when the depth scale 156 is expressed as a white level, as a digital signal at a level representing the white level.
7, the data is captured into the data capture memory 34.

Therefore, the information of one display line is stored in the memory 34,
For example, in the figure, the rightmost end of the memory 34 is the display 8.
The leftmost portion of the memory 34 stores information corresponding to reflection information at a deep position in the selected depth range.

In this example, since 0 to 800m is displayed, Om is on the rightmost side of memory 34, 800m is on the leftmost side, and memory 3 is on the far right side of memory 34.
White information indicating the depth scale is stored at each position obtained by dividing the area between both ends of 4 into 8 equal parts.

Since the time scale 157 is generated in synchronization with the operation of the display 82, the output of the oscillator 83 is generated by the time scale generator 1.
The digital signal is frequency-divided at 59 and is applied to the buffer memory 79 through an OR circuit 94 so as to be at a position corresponding to the lowermost side on the display line, for example, every time two minutes elapse, resulting in a white display.

In the display in Figure 10, O
Display of detection information for a range of ~800m and 400m of that
This is a case where an enlarged display of a portion of ~500 m is displayed in parallel.

The expansion range 400 to 500 is selected by selecting the output of the decoder 58 with the expansion value selection switch 59, and the expansion width, ie, 100 m, is selected with the switch 64.

In the selection reading means 74 and 75, the display width selection switch 92 is set to terminal b so that the selection reading means 74 and 75 are selected and their displays are displayed on the upper half and the lower half, respectively. .

In this case, the information from O to 800 m is captured as one display line segment to the capture memory 34, as in the previous case, and the memory 35 captures the information from 400 to 500 meters as one display line segment. minutes.

The contents of the memory 34 are compressed by the selective reading means 74 and written into the first half of the buffer memory 79, the right half in the figure, and the contents of the memory 35 are compressed and taken into the second half.

Therefore, as shown in FIG. 10, the seabed is displayed as 161 and the school of fish is displayed as 162, and their enlarged views are further enlarged and displayed as the seabed 163 and the school of fish 164.

The depth scale 156 is compressed and displayed as a depth scale 160.

Further, the output of the gate signal generation circuit 61 indicating the enlarged position is supplied to the enlarged mark generator 169, and the display color (for example, white) is displayed at positions corresponding to the rising and falling edges of the gate signal of the gate signal generating circuit 61. The resulting digital signal is taken into the data take-in memory 34 through the OR circuit 57.

As a result, an enlarged position display line 165 indicating the enlarged position is displayed, indicating that this portion is enlarged downward.

Further, the output of the gate signal generation circuit 61 operates the enlarged depth mark generator 166, which divides the output of the frequency divider 13 and generates a depth mark for the enlarged display portion. It is written into the enlarged information acquisition memory 35 through the OR circuit 67 as a digital signal indicating the level corresponding to the displayed color.

As a result, an enlarged depth mark 167 is displayed on the display.

In addition, in order to provide a boundary line 168 that indicates the boundary between the normal display in the upper half and the enlarged display in the lower half, the output of the read counter 91 of the selection reading means 74 passes through the OR circuit 169 and further passes through the OR circuit 94 to the buffer memory 79. written to.

Similarly, when the selective reading means 74 to 77, etc. are selected, the output of the reading counter 91 of the selective reading means is supplied to the OR circuit 169, and the signal indicating the boundary of the display is used as a boundary line signal. buffer memory 79
written to.

Furthermore, in this example, 11 minutes before the current time, the normal display remains at 5, the enlargement switch 64 is selected, the enlargement rate is set to dog, the width is enlarged to 50m, the enlargement position selection switch 59 is selected, and the range from 550m to 600m is set. This is a case where the area between the two images is selected to be enlarged.

As a display example, as shown in FIG. 11, 20 minutes before the current time, the normal display of 0 to 600 m is selected by the selection switch 14, and then the part of 500 to 600 m is selected by the enlarged position selection switch 59, and then selected. This is a case where the reading means 74 and 75 are selected and displayed, and a seabed display 161 and a school of fish 162 are displayed as a seabed 163 and a school of fish 164, respectively, in an enlarged display.

Selection reading 1,000 steps 74 and selection reading means 76 for seafloor expansion
, further select the selection reading means 77, 78 for net height meter information, and press the display width selection switch 9 for each of these.
2 to terminal C.

In this way, the buffer memory 7
9, the information of each of the memory 34 and memories 36, 46, and 47 is compressed into h pieces and written.

Therefore, the upper 1/4 portion of the display screen is normally displayed, and the seabed 171 and fish school 172 are displayed, and the display from the seafloor enlarged data acquisition unit displays the seabed in the next 1/4 portion. A display line 173 shown is displayed as a straight line, and a display 174 corresponding to the school of fish 172 appears above it.

Further, in the upper half of the lower half of the display screen, a display above the net height meter appears, and a display 175 indicating the position of the net height meter appears.
A school of fish 176 is displayed above it, and a seabed 177 and a school of fish 178 are displayed further below based on the lower information of the net height meter.

As described above, according to the image display device according to the present invention, display can be performed in various display modes by selecting the selective reading means, and in this case, priority can be given by providing selection circuits for the selective reading means in series. The items that can be displayed are ranked according to their priority, and for example, in the embodiment shown in FIG. 1, even if all the selected reading means are selected, the first selected reading Depending on the setting state of the stage 74, it is determined whether or not the selected reading means can read and display the information thereafter.In other words, if the switch 92 is set to the full-width display terminal a, information from other selected reading means will not be selected. It is not displayed regardless of whether it is present or not.

In addition, in the case where the selective reading stage 74 is set to the half width terminal b, the selective reading means 75 to 78
Selective reading 75 or 76 depending on the selection state inside
Information from and will be selectively displayed.

The determination of this priority order is not limited to the above example, and can be arbitrarily selected.

Further, the amount of data to be displayed can be increased or decreased.

Furthermore, this invention is useful not only for displaying fish finders, but also for displaying data on a cathode ray tube display of other similar detection and recorders using ultrasonic waves, which have a relatively slow information speed. It can be applied when enlarging, reducing, or displaying related data, and by prioritizing the selection of such display modes, these can be displayed without confusion. .

[Brief explanation of the drawing]

1 to 3 are book diagrams separately showing an example of the image display device according to the present invention, FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 is a screen height meter. FIG. 6 is a block diagram showing an example of the selection circuit, FIG. 7 is a waveform diagram for explaining its operation, and FIG. 8 is a diagram showing the state of data transfer from the buffer memory to the main memory. FIG. 9 is a waveform diagram showing an example of a received signal of a screen height meter, and FIGS. 10 and 11 are diagrams showing examples of display on each display.

Claims (1)

[Claims] 1. A plurality of data acquisition memories of the same capacity into which data is periodically acquired, and respective selection circuits provided corresponding to these data acquisition memories and connected in cascade, and the selection circuits are selected. When the clock is not selected, the read clock generation circuit operates, generates a predetermined number of clock signals from the start signal, reads the corresponding data acquisition memory, and sends the read end signal to the next stage selection circuit as a start signal. selective reading means for passing the activation signal to the next stage selection circuit; an OR circuit for ORing the read data of the data acquisition memory taken out by these selective reading means; and the data for the data acquisition memory. A synchronization detection circuit which applies a start signal to the first stage of the cascade-connected selection circuits each time the acquisition of the data is completed, and the selection readout means are respectively provided, and means for selecting the readout clock frequency and the output of the OR circuit are written. The output of the OR circuit operates in synchronization with the write signal of the synchronization detection circuit and the output of the OR circuit at almost the same speed as the slowest of the readout clock signals generated from the selection readout means. a buffer memory control means for writing data into the buffer memory, a cathode ray tube display device, and a storage capacity for one screen of the cathode ray tube display device, and read out in synchronization with scanning of the display screen of the cathode ray tube display device;
A main memory supplies the readout output as a display image signal to the cathode ray tube display device, and the contents of the buffer memory are transferred to a predetermined line on the display screen in synchronization with a surface synchronization signal of the cathode ray tube display device. The data is transferred to the storage location of the main memory to be displayed as one display line on the scanning line, and the timing of reading out the content already stored in the main memory is set relative to the surface synchronization signal by the line scanning period. and control means for shifting the display on the line scanning lines on the display screen sequentially to older display lines.