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JPS6144963U - Synchronous signal compression separation circuit - Google Patents

Synchronous signal compression separation circuit

Info

Publication number
JPS6144963U
JPS6144963U JP12837784U JP12837784U JPS6144963U JP S6144963 U JPS6144963 U JP S6144963U JP 12837784 U JP12837784 U JP 12837784U JP 12837784 U JP12837784 U JP 12837784U JP S6144963 U JPS6144963 U JP S6144963U
Authority
JP
Japan
Prior art keywords
signal
circuit
separation circuit
synchronization signal
single level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12837784U
Other languages
Japanese (ja)
Other versions
JPS646612Y2 (en
Inventor
和雄 望月
邦男 岩井花
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP12837784U priority Critical patent/JPS6144963U/en
Publication of JPS6144963U publication Critical patent/JPS6144963U/en
Application granted granted Critical
Publication of JPS646612Y2 publication Critical patent/JPS646612Y2/ja
Granted legal-status Critical Current

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  • Synchronizing For Television (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の回路図、第2図は第1図の
一部回路の一実施例の詳細な回路図、第3図は複合カラ
ーテレビジョン信号の説明図である。 1・・・・・・複合カラーテレビジョン入力端子、2・
・・・・・A/D変換器、3・・・・・・Y/C分離回
路、4・・・・・・同期信号を単一レベルに固定する回
路、6,8・・・・・・各種信号処理回路、9・・・・
・・同期分離回路。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of an embodiment of a part of the circuit shown in FIG. 1, and FIG. 3 is an explanatory diagram of a composite color television signal. 1...Composite color television input terminal, 2.
...A/D converter, 3...Y/C separation circuit, 4...Circuit for fixing the synchronization signal to a single level, 6, 8...・Various signal processing circuits, 9...
...Synchronization separation circuit.

Claims (1)

【実用新案登録請求の範囲】 1 デイジタルテレビジョンにおいて、複合カラーテレ
ビジョン信号をA/D変換した後輝度信号と色信号とに
分離するY/C分離回路と、Y/C分離回路から輝度信
号を入力し同期信号を単一レベルに固定する回路と、こ
の同期信号を単一レベルに固定する回路からの出力に対
して輪郭強調、走査線変換等の各種信号処理を施した後
あるいは前記信号処理中に前記単一レベルに固定した同
期信号を抽出する同期分離回路とを具備することを特徴
とする同期信号圧縮分離回路。 2 前記同期信号を単一レベルに固定する回路は、前記
輝度信号の有効範囲、に対して1から最大量子化レベル
までを割当て、前記同期信号に対しては量子化レベルゼ
ロを割当てることを特徴とする実用新案登録請求の範曲
第1項記載の同期信号圧縮分離回路。
[Claims for Utility Model Registration] 1. In a digital television, a Y/C separation circuit that separates a composite color television signal into a luminance signal and a color signal after A/D conversion, and a luminance signal from the Y/C separation circuit. A circuit that inputs the synchronization signal and fixes it to a single level, and a circuit that fixes the synchronization signal to a single level.The output from the circuit that fixes the synchronization signal to a single level is subjected to various signal processing such as edge enhancement and scanning line conversion, or A synchronization signal compression and separation circuit comprising: a synchronization separation circuit that extracts the synchronization signal fixed to the single level during processing. 2. The circuit for fixing the synchronization signal to a single level assigns a quantization level from 1 to a maximum quantization level to the effective range of the luminance signal, and assigns a quantization level of zero to the synchronization signal. 1. A synchronizing signal compression/separation circuit as set forth in Paragraph 1 of the utility model registration claim.
JP12837784U 1984-08-24 1984-08-24 Synchronous signal compression separation circuit Granted JPS6144963U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12837784U JPS6144963U (en) 1984-08-24 1984-08-24 Synchronous signal compression separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12837784U JPS6144963U (en) 1984-08-24 1984-08-24 Synchronous signal compression separation circuit

Publications (2)

Publication Number Publication Date
JPS6144963U true JPS6144963U (en) 1986-03-25
JPS646612Y2 JPS646612Y2 (en) 1989-02-21

Family

ID=30687005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12837784U Granted JPS6144963U (en) 1984-08-24 1984-08-24 Synchronous signal compression separation circuit

Country Status (1)

Country Link
JP (1) JPS6144963U (en)

Also Published As

Publication number Publication date
JPS646612Y2 (en) 1989-02-21

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