JPS60139376U - Vertical synchronization signal enhancement circuit - Google Patents
Vertical synchronization signal enhancement circuitInfo
- Publication number
- JPS60139376U JPS60139376U JP2525784U JP2525784U JPS60139376U JP S60139376 U JPS60139376 U JP S60139376U JP 2525784 U JP2525784 U JP 2525784U JP 2525784 U JP2525784 U JP 2525784U JP S60139376 U JPS60139376 U JP S60139376U
- Authority
- JP
- Japan
- Prior art keywords
- vertical synchronization
- video signal
- synchronization signal
- circuit
- signal enhancement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
- Color Television Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す構成図、第２図はその
説明のための波形図、第３図はその具体回路図である。FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the same, and FIG. 3 is a specific circuit diagram thereof.
Claims (1)
む映像信号処理回路に供給されると共に、上記入力映像
信書が上記垂直同期分離回路の時定数より大きな時定数
を有する他の垂直同期分離回路に供給され、この他の垂
直同期分離回路の分離出力が上記加算回路で上記入力映
像信号に、加算されることを特徴とする垂直同期信号強
調回路。The input video signal is supplied to a video signal processing circuit including a vertical synchronization separation circuit via an adder circuit, and the input video signal has a time constant larger than the time constant of the vertical synchronization separation circuit. , and the separated output of another vertical synchronization separation circuit is added to the input video signal by the addition circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2525784U JPS60139376U (en) | 1984-02-24 | 1984-02-24 | Vertical synchronization signal enhancement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2525784U JPS60139376U (en) | 1984-02-24 | 1984-02-24 | Vertical synchronization signal enhancement circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60139376U true JPS60139376U (en) | 1985-09-14 |
Family
ID=30520162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2525784U Pending JPS60139376U (en) | 1984-02-24 | 1984-02-24 | Vertical synchronization signal enhancement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60139376U (en) |
-
1984
- 1984-02-24 JP JP2525784U patent/JPS60139376U/en active Pending
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