JPS60135868U - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS60135868U JPS60135868U JP2312384U JP2312384U JPS60135868U JP S60135868 U JPS60135868 U JP S60135868U JP 2312384 U JP2312384 U JP 2312384U JP 2312384 U JP2312384 U JP 2312384U JP S60135868 U JPS60135868 U JP S60135868U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- processing circuit
- synchronization signal
- signal processing
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案実施例の回路ブロック図、第２図はＡ／
Ｄ変換器への入力映像信号を示す図である。第３図は従
来例におけるＡ／Ｄ変換器への入力映像信号を示す図で
ある。
主な符号の説明、１・・・同期信号圧縮回路、７・・・
同期信号伸張回路。Fig. 1 is a circuit block diagram of an embodiment of the present invention, Fig. 2 is an A/
FIG. 3 is a diagram showing an input video signal to a D converter. FIG. 3 is a diagram showing an input video signal to an A/D converter in a conventional example. Explanation of main symbols, 1... Synchronization signal compression circuit, 7...
Synchronous signal expansion circuit.
Claims (1)
て時間軸圧縮又は伸張した上でＤ／Ａ変換する映像信号
処理回路において、前記Ａ／Ｄ変換の前段において前記
同期信号の比率を圧縮する同期信号圧縮回路と、前記Ｄ
／Ａ変換の後段において前記同期信号を元の比率に伸張
する同期信号伸張回路とを備えることを特徴とする映像
信号処理回路。In a video signal processing circuit that A/D converts a video signal, performs time axis compression or expansion based on a synchronization signal of opposite polarity, and then performs D/A conversion, the ratio of the synchronization signal is determined in a stage before the A/D conversion. a synchronization signal compression circuit for compressing, and the D
A video signal processing circuit comprising: a synchronization signal expansion circuit that expands the synchronization signal to its original ratio at a subsequent stage of /A conversion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2312384U JPS60135868U (en) | 1984-02-20 | 1984-02-20 | Video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2312384U JPS60135868U (en) | 1984-02-20 | 1984-02-20 | Video signal processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60135868U true JPS60135868U (en) | 1985-09-09 |
Family
ID=30516070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2312384U Pending JPS60135868U (en) | 1984-02-20 | 1984-02-20 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60135868U (en) |
-
1984
- 1984-02-20 JP JP2312384U patent/JPS60135868U/en active Pending
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