JPS6135568A - Gate protecting diode - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a gate protection diode for an insulated gate field effect semiconductor device, such as a protection diode for protecting the gate electrode of an MO8 type semiconductor device from surge input.

[Technical background of the invention]

Japanese Patent Publication No. 43-455 was the first to disclose an insulated gate type field effect semiconductor direct gate protection diode, and the protection diode disclosed therein generally has the structure shown in FIG. 2, for example. In the figure, 1 is a P-type silicon substrate. There is an N-type inert region on the surface layer of the silicon substrate.
A region 2 is formed, and the junction therebetween constitutes a protection diode. This N-type impurity region 2 is connected to an input pad via a wiring tea, and is also connected to a gate electrode of a MOS l-transistor formed in another region of the silicon substrate 1.

In the MO8 type semiconductor device in which a protection diode is interposed between the input pad and the gate electrode in this way, if a surge voltage greater than the reverse withstand voltage of the protection diode is input, the diode will cause avalanche breakdown. A current flows through the substrate 1. Therefore, no surge voltage is applied to the gate electrode of the MOS transistor, making it possible to avoid genit breakdown.

However, since the protection diode shown in FIG.
The joint part, that is, the part marked with an X in the figure, has a locally low reverse breakdown voltage (Grove; Physics
nd Tedhnology of 5eaico
ndductordevices, P, 197)
. As a result, the breakout current concentrates at the junctions in this surface area, which has a low withstand voltage, and there is a problem in that the current collectors are prone to thermal breakdown called second breakdown, resulting in permanent breakdown of the junctions. IET
rans, on E 1eCtron D evi
ce, LL bibile, Lp, 763-770 and 12
th, Ann, Proc, Int, Re1.
phys, SVn+D, 1984 1), p, 3
04-312). However, as the depth of the diffusion layer becomes shallower with the miniaturization of elements, this problem becomes more pronounced.

Therefore, in order to improve the above-mentioned problems, the structures shown in FIGS. 3 to 5 have been conventionally adopted.

In the structure shown in FIG. 3, an electrode 4 is formed which is widely overlaid on the junction of the N-type impurity region 2 on the silicon substrate surface via an insulator 113, and a voltage having the same potential as the input is applied to the electrode 4. This is what I did. In this structure, electrode 4
As a result, the depletion layer near the surface is widened due to the field plate effect caused by the field plate effect, and as a result, the electric field concentration near the surface is relaxed and the reverse breakdown voltage of the junction is improved (I E3.
Trans, onE! ectron Device,
Lm once, , ri, l), 157-162) The structure in Figure 4 is an N-type inert region IP! N-type region 2' around the entire periphery of 2
The N-type impurity region constituting the diode has a double diffusion structure.

In such a double diffusion structure, the depletion layer extends inside the N-type region, so the electric field applied to the junction is relaxed and the withstand voltage is improved.

In the structure shown in FIG. 5, only the junction near the surface where the withstand voltage is the lowest in the protection diode shown in FIG. 2 is made into an N-/N" double diffusion structure to improve the withstand voltage.

[Problems with background technology]

The structures shown in Figures 3 to M5 are effective to a certain extent in preventing permanent damage caused by local block-down and current concentration of the brainer junction constituting the protection diode, but none of them are effective. It includes the following problems:

In other words, as a result of these structures improving the reverse withstand voltage of the protection diode, breakdown does not occur even when a surge input of a predetermined voltage or higher occurs, and the protection diode is no longer able to fulfill its original function. .

Furthermore, in the structures shown in FIGS. 3 and 4, the withstand voltage near the surface is still relatively low, so it is not necessarily sufficient to avoid concentration of breakdown current.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a gate protection diode formed on the same semiconductor substrate for protecting an insulated gate field effect semiconductor device from surge input. The present invention provides a gate protection diode that has a reverse withstand voltage sufficient to perform its protective function and does not cause current concentration at the junction near the surface of the substrate that would cause permanent breakdown of the junction. be.

[Summary of the invention]

In order to achieve the above object, the present invention lowers the reverse breakdown voltage at the bottom of the planar junction constituting the gate protection diode, and also reduces the rise in reverse breakdown voltage at the surface, so that the breakdown current passes through a wide area of the bottom of the planar junction. In addition to preventing current concentration, a suitable reverse breakdown voltage was created.For this purpose, a high-concentration diode with the same polarity as the substrate and in contact with the bottom surface of the Brenna junction that constitutes the protection diode was designed to prevent current concentration. An impurity region was formed.

That is, the gate protection diode according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the surface layer of the semiconductor substrate, and a second conductivity type impurity region in contact with and below the bottom surface of the second conductivity type impurity region. a first conductivity type AA degree impurity region formed in the first conductivity type impurity region, a wiring layer connecting the second conductivity type impurity region to an input pad, and an insulated gate field effect transistor formed in another region of the semiconductor substrate. The device is characterized in that the gate electrode is provided with a wiring layer that connects and connects the second conductivity type impurity region.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 is a sectional view showing a gate protection diode according to an embodiment of the present invention. In the figure, 11 is a P-type silicon substrate, and 12 is an N+ type impurity region. A P+ type impurity region 13 is formed below the N+ type impurity region 12 and in contact with the bottom surface thereof. The concentration of the P-type impurity region 13 is set to be one to two orders of magnitude higher than that of the substrate.

Further, the N1 type region 12 is connected to the input pad via the wiring layer, and the N1 type region 12 is connected to the input pad via the wiring layer, and the M
Connected to the gate electrode of the OS transistor.

The Brehner junction between the N-type impurity region 12 and the surrounding P-type region constitutes a protection diode, and the protection diode has the same input protection function as explained in FIG. Demonstrate one's abilities.

In the gate protection diode of the above embodiment, the P1 type impurity region 1 is in contact with the bottom surface of the Brainer junction of the N+ type impurity region 12.
Since the IIT 13 is provided, the reverse withstand pressure of the bottom surface of the brainer joint is much lower than that of a normal brainer (structure) as shown in FIG.

The reduction in breakdown voltage caused by this P+ type region 13 is determined by the impurity concentration of the region 13. According to various previously reported devices, by setting the concentration of the P+ type impurity region 13 one to two orders of magnitude higher than the substrate concentration as in the above embodiment, the withstand voltage at the bottom of the junction can be increased to that of the junction surface. It is quite possible to make the breakdown voltage lower than the breakdown voltage. In this way, in the protection diode of the above embodiment, the breakdown voltage at the bottom of the junction is lower than the breakdown voltage at the junction surface, so the breakdown current flows through a wide area at the bottom of the Brenna junction, and instead of flowing through a narrow line on the junction surface as in the conventional case. It does not flow through the realm. Therefore, permanent destruction of the bond due to the application of a surge is significantly suppressed for the following reasons.

Generally, when a breakdown current flows locally in the surface layer of a brainer junction, the current will further concentrate in the area where the temperature has increased due to the breakdown current generated by the current. In a brainer joint having a general structure as shown in FIG. 1, this current concentration occurs in a narrow linear region on the joint surface, and therefore joint breakdown is likely to occur. In contrast, in the above embodiment, the breakdown current flows through a wide area of the bottom surface of the junction, so the current threshold at which thermal breakdown of the junction occurs due to positive feedback is large, and therefore even when the same surge voltage is applied. Permanent destruction of the joint becomes less likely to occur.

Further, the embodiment shown in FIG. 1 does not have the problems that occur in the conventional example shown in FIGS. 3 to 5. That is, in the structures shown in FIGS. 3 to 5, the reverse breakdown voltage of the diode as a whole is high, so that breakdown does not occur even when a surge higher than a predetermined voltage is applied.

Although there is a possibility that it will no longer fulfill its original purpose as a protection diode, in the case of the above example, the reverse withstand voltage at the bottom of the Brenna junction is lowered to an appropriate voltage, so the gate protection function is fully demonstrated. It has the advantage of being able to

Next, a method for forming a structure characteristic of the above embodiment will be explained. This structure is, for example, shown in FIGS.
It can be formed as shown in D). First, as shown in FIG. (
(Illustrated in FIG. 6(B)). Next, the N4 type impurity region, L
ii! By selectively implanting boron ions under conditions such that the center of distribution is located slightly below 12', and then thermally diffusing at high temperatures, the embodiment of FIG. 1 has the characteristics shown in FIG. 6(D). structure can be formed.

FIG. 7 is a sectional view showing a gate protection diode according to another embodiment of the present invention. In this embodiment, the present invention is applied to the conventional structure shown in FIG. It has a double diffusion structure. The rest of the structure is the same as the embodiment shown in FIG. In the embodiment shown in FIG. 7, the withstand voltage at the surface layer of the Brainer junction is higher than that in the embodiment shown in FIG. It is possible to satisfy the relative pressure requirements by lowering the breakdown voltage of the bonded surface layer to be lower than that of the bonded surface layer. Furthermore, even when the diffusion depth is shallow and the breakdown voltage of the junction surface layer is low, the reverse breakdown voltage of the protection diode can be set to an appropriate value by changing the degree and shape of the N-type region 14. .

FIG. 8 shows a further structure in which the present invention is applied to the conventional structure shown in FIG.
jJ' is a cross-sectional view showing an embodiment of N+ type impurity region 12.
An N-type region 14' is formed only around the surface layer. This embodiment also provides the same effect as the embodiment shown in FIG. 7, and in particular, the concentration of the P+ type impurity region 13 can be lower than that in the case shown in FIG. - Although the above embodiments all use a P-type substrate,
It goes without saying that the gate protection diode of the present invention can be similarly constructed using an N-type substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a gate protection diode according to an embodiment of the present invention, FIG. 2 is a sectional view showing the most basic structure of a gate protection diode, and FIGS. 2
A cross-sectional view showing a conventional gate protection diode with an improved structure shown in the figure, and FIGS. ,
7 and 8 are cross-sectional views of gate protection diodes according to embodiments of the present invention, respectively. 11...P-type silicon substrate, 12.12'...N+
Type impurity region, 13...P+ type impurity region, 14°1
4'...N-type impurity region. Applicant's agent Patent attorney Takehiko Suzue Figure 1, Figure 1. Figure isFigure 6Figure 1NINilil illiH

Claims (1)

[Claims] A first conductivity type semiconductor substrate, a second conductivity type impurity region formed on the surface layer of the semiconductor substrate, and a first conductivity type impurity region formed below and in contact with the bottom surface of the second conductivity type impurity region. The second conductivity type impurity is applied to a concentrated impurity region, a wiring layer connecting the second conductivity type impurity region to an input pad, and a gate electrode of an insulated gate field effect transistor formed in another region of the semiconductor substrate. A gate protection diode characterized by comprising a wiring layer connecting regions.