JPS6114764A - Insulated gate field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor, and more particularly to an insulated gate field effect transistor incorporating a protection diode for preventing electrical breakdown of the gate. Due to the structure of an insulated gate field effect transistor, when a high voltage is applied to the gate, the gate insulating film is destroyed -1- 07/
'I have something to do. This dielectric breakdown phenomenon occurs not only when a high voltage is intentionally applied to the gate, but also when static air is charged. Therefore, some devices have a built-in diode for protection to prevent dielectric breakdown. FIG. 1 is a schematic cross-sectional view of a conventional insulated gate field effect transistor incorporating a protection diode. In the eleventh column, 1 is a P-type semiconductor substrate, which is a so-called n-channel MOS F' E 1
' is an example. Gate i11. fftio is connected to the ohmic electrode 14 of the active diode by the ohmic metal 12 and wiring metal. The junction of the diode for protection is formed by 4 of P and 5 of n and 10. This P
The breakdown voltage of the +n junction is meaningless unless the dielectric breakdown of the gate is less than 1 voltage, and it cannot function as a transistor unless it is in the voltage range normally applied to the gate, for example, 0 to 20 V or more. The breakdown voltage of a Pn junction is related to the impurity concentration or the depth of the junction. Conventional P
By controlling the impurity concentration in region 4 or by diffusion,
The breakdown voltage was controlled by such methods as selecting the spacing between regions 4 and 5 so that the impurity concentration would be optimal when the and n regions extended laterally and collided with each other. As mentioned above, the conventional insulated gate field effect transistor as shown in FIG. 1 has the following characteristics.

(1) It is necessary to form the P region 4, which increases the number of steps.

(2) Since it is necessary to control the impurity concentration of the P region 4 and requires advanced technology, it becomes expensive and also reduces the yield.

(3) Since the gate dielectric breakdown voltage depends on the thickness of the gate insulating film 6, it is necessary to change the conditions for forming the region 4 for each model with a different film thickness.

The present invention provides a novel structure of an insulated gate field effect transistor that solves the above-mentioned drawbacks of the conventional type, and provides an inexpensive and highly reliable insulated gate field effect transistor that can simplify the structure and manufacturing process. can be obtained.

The present invention will be explained in detail below using the drawings.

[Example 1] FIG. 2 is a cross-sectional structural diagram showing an example of the present invention, and FIGS. 3 a) to 3 d) schematically show the manufacturing process thereof. Third
Figure a) shows a state in which an oxide film is selectively formed in the peripheral area by a well-known method such as thermal oxidation, photographic processing, and etching. In b), a gate oxide film was formed by a well-known method on a portion where no oxide film was formed. C) is a gate type ITO and a second gate electrode 16 formed by laminating an electrically conductive film on the protective diode region with an insulating film interposed therebetween, which is a feature of the present invention.

In this example, polysilicon is formed on the entire surface using the usual CVD method, and then is subjected to normal photo processing.

It was formed by ching. Using this polysilicon as a mask, the gate oxide film is removed by etching, and the drain 2
, the source 3 and the n-region 5 of the protection diode are formed. At this time, phosphorus is also diffused into the polysilicon, and the resistance I1^ of the polysilicon decreases to a resistance value sufficient for use as an electrically conductive film for a gate. the? When a metal for an ohmic electrode, such as AI, is formed by a conventional LA method, the result is as shown in FIG.

Although the gate electrode 12 and the electrode 14 of the protective diode are not particularly shown, it is preferable to connect them on the surface with AI wiring, and the source electrode 13 should be electrically connected to the second gate electrode 16. is necessary.

In this example, the thickness of the insulating film 6 (gate oxide film) is 110 mm.
A voltage was applied between the source and the protection diode with the source short-circuited to the substrate 1, and the breakdown voltage of the protection diode was examined and found to be about 35V. It has been separately confirmed that the gate insulating film 6 has a breakdown voltage of 50V or more.

Furthermore, it was confirmed that the gate applied voltage of this type of field effect transistor is in the range of 0 to 20 V, which is optimal as the breakdown voltage of the protective diode. Furthermore, when the gate oxide film thickness is 80 nm and 200 nm, the dielectric breakdown voltage is 40 V or more and 100 V or more, respectively, whereas the breakdown voltage of the interlocking diode automatically changes to about 32 V and 40 V, respectively. was confirmed. Furthermore, it has been confirmed that the breakdown voltage in each case has nothing to do with the impurity concentration of the P-type substrate 1 and is related only to the thickness of the insulating film 6' under the second gate electrode 16. For example, if the thickness of the insulating film 6° (oxide film) is constant at 120 nm, the impurity concentration of the P-type substrate 1 is changed from approximately 5x10'cI11' to 2X1o5't.
When experiments were carried out by changing the voltage, the breakdown voltage was constant at about 36 .ANG. The reason why the above-mentioned phenomenon occurs regarding the breakdown voltage is presumed to be as follows. In order to explain this, FIG. 4 is an enlarged view of the protective diode portion of FIG. 2.

When a voltage is applied between the source and the gate, the protective diode is reverse biased and a depletion layer shown at 17 is formed. The width of the depletion layer is narrower near the first surface due to the planar junction, but on the side where the second gate electrode 16 is located (4)
Since 16 is short-circuited with the source, it becomes a ground potential, suppressing the expansion of the depletion layer. Therefore, the depletion layer becomes much narrower than in the case (I3) without the second gate electrode 16, and breakdown occurs at a lower voltage. The effect of this second gate electrode in suppressing the spread of the depletion layer is determined not by the degree of impurity in the substrate 1 but by the thickness of the insulating film, that is, the oxide film, similar to the channel formation by the gate electrode of the MOS FET. It is believed that the phenomenon of the present invention is based on the above reasons. The second gate electrode 16 may cover the entire exposed surface of the PN junction of the protection diode, but if the PN junction has even one weak spot, breakdown will occur from that spot. Therefore, the second gate electrode 16 only needs to be formed in a portion.

[Example 2] FIG. 5 shows an example in which the present invention is applied to a vertical MO8FBT (hereinafter abbreviated as vDMO8). In VDMO8, a portion corresponding to the base region 1 of [Example 1] is formed of a diffusion layer, and a low concentration base region 1 necessary for channel formation and a high concentration base region 1 necessary for forming a channel and a high concentration for improving resistance to high voltage and ohmic resistance are formed. It consists of a deep diffusion region 18. When a protective diode is formed using the conventional method, the high concentration region 1
If the n region for the diode is formed within the region 8, the breakdown voltage of the diode will be too low (usually 5 to SV), and if it is formed only within the low concentration P region 1, the breakdown voltage will be too high to be useful. (usually 50-100V). In the present invention, by forming the n+ region 5 in the lightly doped P-type region 1 and providing the second gate itt and ff116, it was possible to obtain the optimum breakdown voltage as in [Embodiment 1].

Although the explanation has been given above regarding the n-channel type using the P-type substrate region 1, it goes without saying that the present invention can also be applied to the P-channel type using the n-type substrate.

In other words, uniform conductivity type conversion is also included in the scope of the present invention.

As described above, the present invention! '! ! Edge-gate field effect transistors have a protective diode that implodes to effectively prevent electrical breakdown of the gate, simplify the structure and manufacturing process, and provide low-cost and highly reliable transistors.
This is extremely effective in industry.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of a conventional insulated gate field effect transistor, a VGZ diagram and FIG. 5 are cross-sectional structural diagrams of an embodiment of the present invention, and FIG. 3 is a manufacturing process diagram for the embodiment of FIG. FIG. 4 is an enlarged structural diagram of the protective diode portion of FIG. 2. 1 is a conductor substrate, 2 is a drain region, 3 is a source region, 4 is a region of the same conductivity type as the substrate of the protection diode, 5
11.1 is the base of the protection diode and the reverse conduction w1 type region, 6 is the main gate insulating film, 6 is the second gate insulating film, 7.8 and 9 are the passivation insulating films, 10 is the main gate electrode, 11.1
2.13.14 and 15 are ohmic wire meshes, 16 is a second gate electrode, 17 is a depletion layer, and 18 is a high concentration region. Patent Applicant Shindengen Kogyo Co., Ltd. -37: D G-9 Rod 1 Mouth 2nd Prisoner Figure 5

Claims (1)

[Claims] A source, a drain, and a protective diode region having the same conductivity type are formed on one surface of a semiconductor substrate, and at least a part of the portion of the protective diode region where the PN junction is exposed on the one surface is formed on an insulating film. An insulated gate field effect transistor characterized by being covered with a second gate electrode made of a laminated electrically conductive film, and the second gate electrode is electrically connected to the source region.