JPH02238668A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress gate breakdown of an FET constituting a protective element for preventing electrostatic breakdown of an LSI by connecting the drain of the electrostatic breakdown protective element to an input wiring, the source thereof to a power source wiring, and the gate thereof to a well. CONSTITUTION:A p<-->-type well 13 is formed in an element forming region in a separating oxide film 12 formed on a p<-->-type Si substrate or a p<-->-type epitaxial layer 11. Then, a gates 15, 15A are formed on the well 13 via a gate oxide film 14, and an n<+>-type drain 16, sources 17, 17A are formed to have LDD structure in the well 13, and p<+>-type well contact regions 18, 18A, 22 are formed in the well 13. The gates 15, 15A are connected to the well 13 at a contact hole 24 by a wiring 23 via contact holes 25, 25A. Thus, gate breakdown of an FET, constituting a protective element for preventing electrostatic breakdown of an LSI, can be suppressed.

Description

[Detailed Description of the Invention] (Summary) Regarding semiconductor devices having electrostatic discharge damage (ESD) protection elements, in response to the miniaturization of elements, gate destruction of FETs constituting protection elements for preventing electrostatic discharge damage in LSIs has been developed. (1) A well of one conductivity type with a higher impurity concentration than the substrate is formed in the surface layer of a semiconductor substrate of one conductivity type.A channel head area is formed in the surface layer of the well of one conductivity type. A source and a drain of opposite conductivity types separated from each other, a gate on the channel region via a gate insulating film on the surface of the substrate, a well contact region of one conductivity type on the surface layer of the well of the one conductivity type, has an input wiring and a power supply wiring for connecting an input terminal and a human power circuit, the drain or source is connected to the input wiring, and the source or drain and the well contact region are connected to the power supply wiring V,, (
(2) In (1) above, the central region of the source or drain connected to the input wiring; (3) In (2) above, the central part of the source or drain connected to the input wiring is formed in the substrate in the one conductivity type well, or (3) in (2) above, The structure has a well of an opposite conductivity type in contact with the region.

(Industrial Application Field) The present invention relates to a semiconductor device having an electrostatic discharge protection element.

Due to the high integration of LSI and miniaturization in area and thickness direction,
The ESD protection element and the element to be protected have a breakdown voltage of V.
Since the ESD protection element itself becomes easily destroyed due to a decrease in B and a decrease in the withstand voltage of the gate oxide film, a protection element structure is required that prevents the ESD protection element itself from being destroyed and that can reduce the voltage stress to a level below the withstand voltage of the element to be protected. Become.

[Conventional technology]

FE constituting the protection element shown in the equivalent circuit diagram of Fig. 6
In order to prevent the destruction of the gate oxide film of T T+, conventionally,
The product C-17 of the gate-drain capacitance C and the resistance R inserted between the gate and the source was used to alleviate the voltage stress coming from the bat (the input terminal of the LSI).

FIGS. 7(1) and 7(2) are a sectional view and a plan view of an ESC protection element according to conventional example Q.

In the figure, 1 is the substrate, IA is the diffusion layer, 2 is the source/drain electrode connected to the input wiring 5, and 3 is the power supply wiring 6.
The drain/source electrode connected to, 4 is the gate 1~,
5 is the input wiring between the LSI pad and the human circuit. 6 is connected to the power supply wiring 6 via a power supply wiring (Vcc/Vss) and a resistor R through a contact hole 7.

Alternatively, this element may be formed within a well IB formed within the substrate.

Due to the miniaturization of devices, the gate breakdown voltage of FET T is decreasing, and FET T is becoming LDD (Lightly
In the case of a DopedDrain) structure, the depletion layer of the junction expands and the capacitance C decreases, making it insufficient to follow the gate voltage when voltage stress is applied, causing the FET T+ to break down. .

[Problem to be solved by the invention]

In response to the miniaturization of elements, the present invention aims to provide a structure that suppresses gate breakdown of an FET that constitutes a protection element that prevents electrostatic discharge breakdown in LSI.

[Failure to solve the problem]

The above problem can be solved by (1) forming a one-conductivity type well in the surface layer of a one-conductivity type semiconductor substrate with a higher impurity concentration than the substrate; A source and a drain of opposite conductivity types in the surface layer of the well of one conductivity type across a channel region, a gate on the surface of the substrate on the channel region via a gate insulating film, and a surface layer of the well of the one conductivity type. The substrate has one conductivity type well contact region and one input wiring and power supply wiring for connecting an input terminal and an input circuit on the substrate. The drain or source is connected to the input wiring, and the source or drain and the well contact I-region are connected to the power supply wiring v55.
(2) In (1) above. a semiconductor device in which a central region of a source or drain connected to an input wiring is formed in the substrate, and an end region is formed in the one conductivity type well;
Alternatively, (3) in (2) above, this can be achieved by a semiconductor device having a well of an opposite conductivity type in the substrate and in contact with the central region of the source or drain connected to the input wiring.

(Function) The present invention creates a well in a low-concentration substrate that has the same conductivity type as the substrate and has a higher impurity concentration than the substrate, forms a protection element here, connects the gate of the FET to the well, and connects the protection element to the well. When a voltage stress is applied to the input wiring of the gate, the breakdown (aharancier) current of the drain junction flows through the well to the substrate where it escapes, thereby biasing the gate so as to reduce the voltage applied to the gate. This is to prevent destruction.

In addition, a structure is adopted in which the breakdown current flows diagonally from the drain toward the deep part of the well, thereby distributing heat generation locations within the substrate and preventing secondary breakdown of the drain junction.

(Embodiment) FIGS. 1(1) and 1(2) are a sectional view and a plan view of an ESD protection element according to a first embodiment of the present invention.

In the figure, a p-type well 13 is formed in an element formation region within an isolation oxide film 12 formed on a p-type Si substrate or a p''-type shrimp layer 11.

A gate L5 is formed on the well 13 via the gate oxide film 14.
．． 15A is formed.

In the well 13, an n+ type train 16 and a source 171 are provided.
7A is formed with an LDD structure.

A p+ type well contact region 18 within the well 13,
18A, 22 are formed.

Gate 15. 158 are each contact hole 2
It is connected to the well 13 through the contact hole 24 via the wiring 23 via 525A.

Although not shown, the drain electrode 19 is connected to the input wiring of the LSI in the same way as in the conventional example shown in FIG.
．． 20A and well contact electrode 2121A are connected to power supply wiring VSS.

FIGS. 2(1) and 2(2) are a sectional view and a plan view of an ESD protection element according to a second embodiment of the present invention.

The difference from FIG. 1 is that the well 131 has a rectangular shape missing below the drain 16.

The feature of this structure is that breakdown occurs first at a position away from the center of the drain junction, as will be explained with reference to the structure shown in FIG. 3 below, so that heat generation positions are distributed.

FIGS. 3(+) and 3(2) are a sectional view and a plan view of an ESD protection element according to a third embodiment of the present invention.

The difference from FIG. 2 is that there is a well 13 below the drain 16.
The n-type well 26 was formed so that the peripheral portion overlapped with the n-type well 26.

A feature of this structure is that the n-type well 26 disperses the heat generating positions more widely than the structure shown in FIG.

Here, the dotted line indicates the expansion of the depletion layer when voltage stress is applied to the drain electrode 19.

Now, consider the case where a positive voltage stress of 1 is applied to the drain electrode 19 in this embodiment.

At this time, the current flows from the drain 16 to the source 17. 17A
In addition to flowing horizontally, it also flows in the depth direction due to breakdown of the drain junction. Since the substrate or shrimp layer has a low concentration directly under the drain electrode 19, breakdown does not occur, but occurs at a slightly distant position, that is, the peripheral area (A part) of the drain 16. Therefore, the heat generation position is dispersed to the right, thereby preventing the joint from suffering secondary failure.

Also, at this time, the gate of the well contact subregion 22 is biased to a negative voltage due to the breakdown current, resulting in a voltage that does not lead to gate breakdown.

This effect will be explained using FIG. 5.

FIG. 5 shows the relationship between the potential of each part and the amount of heat generated with respect to the distance to the right from the center of the drain electrode 19 shown in FIG.

The figure shows the potential and calorific value distribution between a and b in FIG. 3(2).

Here, ■ is near the substrate surface, and ■ is deep in the substrate (well 13).
1). Further, at each position a, the center C of the drain electrode 19, the right end d of the train electrode 19 is near the left end of the well, and the left end b of the gate e is the left end of the well contact electrode 21.

Also, the voltage of each part VB is the drain junction Aharancier breakdown voltage, vB' is the drain side gate end Breakdown voltage of gated junction V, is the voltage applied to the gate 1. It is.

As mentioned above, the breakdown current flows diagonally across the cross section of the substrate, so the peak of heat generation in the deep part is shifted to the right.

In this example, a more complete protection element is obtained by combining the second or third embodiment and the conventional example.

In the figure, the part above the line A--A represents the present invention, and the part below represents the conventional element, and the contact hole 27 is connected to the human power circuit.

In the embodiment, an n-channel device has been described, but for a p-channel device, the conductivity type of each part may be reversed, and VCC may be used as the power supply wiring.

Further, the structure of each embodiment may be formed into a repeating/repetitive mirror image/ring shape.

〔Effect of the invention〕

As explained above, according to the present invention, in response to the miniaturization of elements, a structure has been obtained that suppresses gate breakdown of an FET that constitutes a protection element that prevents electrostatic discharge breakdown in LSI.

In addition to LSIs using MIS FETs such as twin-tub CMOS that have wells of both conductivity types in the substrate, the present invention
It can also be used to protect bipolar devices.

[Brief explanation of drawings]

Figure 1 (1). (2) is a cross-sectional view and a plan view of an ESD protection element according to a first embodiment of the present invention. Figure 2 (1) is a cross-sectional view and a plan view of an ESD protection element according to a second embodiment of the present invention. Figure 3 (1). (2) is a cross-sectional view and a plan view of the ESD protection element according to the third embodiment of the present invention. FIG. 5 is a diagram showing the relationship between the potential of each part and the amount of heat generated with respect to the distance to the right from the center of the drain electrode. The figure is an equivalent circuit diagram (+), and FIG. 7 (2) is a cross-sectional view and a plan view of a conventional ESD protection element. In the figure, 11 is a p-type Si substrate or a p-type shrimp layer, 12 is an isolation oxide film 13, 131 is a p-type well, 14 is a gate oxide film 15. 15A has a gate 16 and an n-type drain 17. 17A is the source 1.8, 18A is the p-type well contact region 19, and the drain electrode 20. 2OA is the source electrode 2L 21A is the well contact electrode 23 is the wiring 24, 25, 25A, 27 is the contact hole 5 is the input wiring 6 between the LSI pad and the input circuit is the power supply wiring (Vcc/Vss)

Claims (3)

[Claims] (1) A well of one conductivity type having a higher impurity concentration than the substrate in a surface layer of a semiconductor substrate of one conductivity type, and a source and a drain of opposite conductivity type separated by a channel region in the surface layer of the well of one conductivity type; a gate on the channel region on the surface of the substrate via a gate insulating film; a well contact region of one conductivity type on the surface layer of the well of one conductivity type; and input wiring connecting the input terminal and the input circuit on the substrate; a power supply wiring, the drain or source is connected to the input wiring, and the source or drain and the well contact region are connected to the power supply wiring Vss.
1. A semiconductor device, wherein the gate is connected to the well of one conductivity type to a ground potential (ground potential) or Vcc (power supply potential). (2) The semiconductor device according to claim 1, wherein a central region of the source or drain connected to the input wiring is formed in the substrate, and an end region is formed in the one conductivity type well. semiconductor device. (3) The semiconductor device according to claim 2, wherein the substrate has a well of an opposite conductivity type in contact with a central region of the source or drain connected to the input wiring.