JPH01280359A - Insulated gate semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device having a gate protective circuit whose breakdown voltage can be designed easily by a method wherein a diode of the gate protective circuit is formed of a polycrystalline Si layer, of a comparatively low resistance, formed simultaneously with a gate and of a polycrystalline Si layer, of a comparatively high resistance, laminated on it. CONSTITUTION:A well 2 of a second conductivity type is formed on a surface layer of a semiconductor substrate 1 of a first conductivity type; a part of the well 2 between a source layer 3, or the first conductivity type, formed on the surface layer of the well 2 and the substrate 1 is used as a channel formation region; a gate 4 composed of a polycrystalline Si layer of a comparatively low resistance is formed on its surface via a gate insulating film 5; a source electrode 7 is brought into contact with the source layer 3 and the well 2. In addition, one or more pairs of diodes composed of the following two are formed: polycrystalline Si 40, of a comparatively low resistance, which has been formed on an insulating film 51 between a region where the source layer 3 of the substrate 1 exists and a region of a gate pad 80 and whose material is identical to that of the gate 4, polycrystalline Si 9, of a comparatively high resistance, which has been laminated on it and whose conductivity type is opposite; the pair of diodes are connected in series between the source electrode 7 and the gate pad 80 by reversing a forward direction.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides a power MO3FET with a gate protection circuit.
Alternatively, the present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as IGBT).

[Conventional technology]

For example, a P layer is formed on one surface of an N-type silicon substrate, an N-type source layer is further formed in the P layer, and a gate oxide film is placed on top of the P layer to form a channel between the substrate and the NJI. The power vertical MO3FET or IGBT is equipped with an electrode, and the main current flows from the source electrode in contact with the source layer and the P layer to the other side of the substrate. In particular, in the field of car electronics, it is essential to have a gate protection circuit, so bank-to-bank protection diodes are used. Patent Publication No. 58-87873 discloses a polycrystalline S laminated on a substrate.
By introducing impurities into semiconductor layers such as iN, bank-to-bank
A device with a back diode was described, published in Japanese Patent Application Laid-Open No. 5
Publication No. 8-178566 or JP-A-61-2967
No. 70 describes a device in which a bank-to-bank diode is built in by introducing impurities into another region within the substrate.

[Invention tries to solve! ! l! l) Conventional gate protection diodes are formed as Zener diodes by introducing impurities into the semiconductor layer on the substrate or the semiconductor substrate, and the Zener voltage is 5V or less, but the breakdown voltage is usually higher than the required IOV. In order to achieve
It is necessary to form multiple Zener diodes in series in both directions, and the breakdown voltage is single-PN.
Disadvantages include being limited to multiples of the Zener voltage of the junction.

The object of the present invention is to provide an insulated gate semiconductor device having a gate protection circuit whose breakdown voltage can be easily designed, while eliminating the above-mentioned drawbacks.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a well of a second conductivity type on one surface I of a semiconductor substrate of a first conductivity type, and a well of a second conductivity type formed in a surface layer of the well. A gate made of a relatively low resistance polycrystalline silicon layer is provided on the surface of the second conductivity type well portion between the source layer and the semiconductor substrate with a gate insulating film interposed therebetween, and the second conductivity type source is used as a channel formation region. In a gate insulated semiconductor device in which a source electrode is in contact with a layer and a second R-shaped well, a region of a semiconductor substrate where a source layer exists and a gate pad 'iiM
A diode is made of a polycrystalline silicon layer of the same relatively low resistance as the gate material formed on the insulating film between the regions, and a polycrystalline silicon layer of the opposite conductivity type and relatively high resistance laminated on top of it. At least one pair of diodes exists, and the pair of diodes are connected in series between the source electrode and the gate band with their forward directions reversed.

[Effect]

By forming the diode of the gate protection circuit with a relatively low-resistance polycrystalline 5iJi formed at the same time as the gate, and a relatively high-resistance polycrystalline 51 layer laminated on top of the polycrystalline 5iJi layer formed at the same time as the gate, a relatively high resistance polycrystalline 51 layer can be selected to have an arbitrary impurity concentration. A bank-to-bank diode can be obtained with a diode having a down voltage.

〔Example〕

FIG. 1 shows a cross section of a vertical MOS FET according to an embodiment of the present invention, and this cross section is taken along the line A--A in FIG. 2, which is a plan view. Silicon substrates are n-Jil and n゛l! A drain layer 11 is formed, and a p well 2 is diffused on the upper surface of the n-Jil. P well 2 has n source N3.
A gate 4 made of a polycrystalline St layer is formed through a gate insulating film 5 so that the p-well 2 between the exposed part of the drain layer 1 between the base layer 2 and the source layer 3 becomes a channel formation region. It will be established. A window 41 as shown in FIG. 2 is opened in the polycrystalline s+11 of the gate 4, and the M wiring is connected to n0 in the contact hole 61 of the insulating film 6 within the window.
A source electrode 7 is formed in contact with the source N3 and the p-well. In the 41-type MO3FET, the 'r! 1 flow is controlled by a signal input to gate 4. The extension of the gate polycrystalline S1 stone 4 has a contact hole 62 shown in FIG.
Contacting A8, this M wiring is extended to form a gate bonding pad (gate band) 80. The p-well 2 is formed below the gate band 80 in order to expand the depletion layer generated when a reverse voltage is applied between the p-well 2 and the n-711 to increase the withstand voltage. At the same time as the gate 4, an n' polycrystalline 5IN40 is formed on the extension part 21 of this p-well via an insulating film 51, and an insulating g! P-type polycrystalline crystals 5iJi9 that are in contact with each other through contact holes 64 of No. 6 are stacked and patterned. n゛Polycrystalline Sij! 40 and p-type polycrystalline S
p m 9 of two PN junction diodes consisting of i-layer 9
are connected by a wiring 71, one n'rfi 40 is connected to an extension of the source electrode 7 through a contact hole 63, and the other n'rfi 40 is connected to a gate pad 80 through a contact hole 65.
is in contact with the extension of As a result, two PN junction diodes are connected in anti-series to
It will be inserted between +. Therefore, when the gate voltage applied between the gate and the source reaches the breakdown voltage of the PN junction diode, which is determined by the impurity level and thickness of the p-type polycrystalline Si layer 9, depending on the direction of the voltage, One diode breaks down and breaks down between gate and source? It? Since JL flows, no higher voltage is applied, and the gate insulating film 5 is protected from electrostatic breakdown.

This protection circuit can be formed in exactly the same way in an IGBT in which pm is provided below the n-drain N1.

〔Effect of the invention〕

According to the present invention, at least one pair of diodes can be formed by a relatively low resistance polycrystalline Si layer formed simultaneously with the gate and a relatively high resistance polycrystalline S1 layer having an arbitrary impurity concentration and thickness laminated thereon. form a bank-to-bank
By inserting a back diode between the gate and the source, it is possible to protect the winter gate from surge voltage input using a diode with a breakdown greater than IOV. In addition, since the diode is formed within the semiconductor substrate, there is no risk of parasitic elements being generated, and it can be used in power vertical MO3FETs or IGBs with gate protection circuits.
It can be effectively used as T.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the present invention, FIG. 2 is a plan view, and FIG. 1 is a sectional view taken along the line A--A. 1: n-drain layer, 2: p well, 21: prfJ,
3; n' source layer 4; polycrystalline Si gate, 40: n'' polycrystalline SiN, 5: gate insulating film, 6: insulating film, 6L 6
2.63.64.65: Contact hole, 7: Source electrode, 71 Ni-drain electrode, 8: Wiring, 80: Gate pad, 9: P polycrystalline Si layer. 1'・-,\

Claims (1)

[Claims] 1) A second conductivity type well is provided in one surface layer of the first conductivity type semiconductor substrate, and a second conductivity type is provided between the first conductivity type source layer formed in the surface layer of the well and the semiconductor substrate. A gate made of a relatively low-resistance polycrystalline silicon layer is provided on the surface of the well part with a channel formation region via a gate insulating film, and a source electrode is in contact with the first conductivity type source layer and the second conductivity type well. polycrystalline silicon, which has the same relatively low resistance as the gate material, is formed on the insulating film between the region where the source layer of the semiconductor substrate exists and the gate pad region, and the opposite conductive material is laminated thereon. An insulated gate comprising at least one pair of diodes made of relatively high-resistance polycrystalline silicon, the pair of diodes being connected in series between a source electrode and a gate pad with their forward directions reversed. type semiconductor device.