JPS61285558A - Data processor - Google Patents

Abstract

PURPOSE:To add a mechanism to read out automatically an address immediately after it is written by storing said written address after detecting that a writing command to a main memory device is delivered. CONSTITUTION:When data are written to a main memory device 2 from a CPU 1 or an input/output controller 4, a memory address 7 is preserved at an address latch 9 by a memory write command signal 8. A sequence circuit 13 sends a bus request signal 10 to a system bus 51 to acquire the bus using right and transmits the address signal of the latch 9. Then a memory read command 15 is sent to the bus 51 and the device 2 executes a reading operation in response to the command 15. At the same time, the device 2 checks the parity of a parity check generating mechanism 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having a structure in which a mechanism for detecting illegal writing operations to a main memory device can be additionally added.

[Conventional technology]

Figure 3 is a block diagram showing the structure of a conventional data processing device. In Figure 2, (1) is a CFtr device that manages the entire system, (2) is the main storage of this CPtr device, and (3) is a The parity check/generate mechanism for the main storage device (2), (4) is the input/output control device that controls the input/output devices* (Sl) connects the above devices (1) to (4). system bus.

(52) is the same bus control device.

Next, the operation will be explained.

The functions of the data processing device include a function (write operation) to write data processed by the CPU (11) and data processed and generated by the input/output control device (4) to an arbitrary address in the main storage device (2); (2) There is a function (read operation) that reads data from an arbitrary address and imports it into the CPU (11) or sends it to the input/output control device (4ν).
In 3), the parity generation circuit is enabled, a parity bit is generated based on the data sent to the system bus (51), and the parity bit is generated in the main memory device (2) at the corresponding address.
1 is stored at the same time as the write operation is completed. During a read operation, the parity bit is also read and the parity information generated from the read data is compared with the stored parity bit. If the comparison results match, it means that the write and read operations were performed safely and accurately, and processing continues; however, if they do not match, a parity error occurred and data processing is interrupted. will be interrupted and transition to an error state, requiring system-wide countermeasures.

[Problem that the invention seeks to solve]

Since conventional data processing devices are configured with two or more units, the moment when a parity error occurs is naturally limited to the read operation, so even if the cause of the parity error is in a write operation, the address The sheller will not be noticed unless the main memory is read, and if a parity error occurs at the time of reading, the problem must be resolved by estimating various environmental conditions at the moment of the previous write operation and detecting the write failure. There were disadvantages such as the need to find the cause and the need for a long time to resolve the problem.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by providing a read-after-write mechanism that can be connected to a data processing device as necessary, it prevents unauthorized write operations. An object of the present invention is to provide a data processing device having a structure that can shorten the time required to resolve a problem.

[Means for solving problems]

This invention provides a data processing device with a read-after-write mechanism that can be connected as needed, and the read-after-write mechanism detects when a write command to the main storage device is output to the main storage device. and a function to automatically read out the written address immediately after writing by storing the written address.

[Effect]

According to this invention, when the read-after-write mechanism is connected to a data processing device, when writing to the main storage device is performed, it immediately detects this and stores the write address. A memory read operation is performed using the ``Memory Read'' operation, and a parity check operation is performed at the same time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, tubes (1) to (5) are the same as in FIG. 3. (61 indicates the entire read-after-write mechanism attached to this data processing device.

(7) is a main memory (memory) address signal generated when the main memory (2) is read/written from the CPU device (1) or the input/output control device (4), and (8) is the main memory (
(memory) write command signal, (9) is the main memory (memory) address signal latch, and α1 is this read after command signal.
H is a bus response signal that is returned in response to the bus request signal when the write mechanism is allowed to use the bus by the system bus (51). System bus controller (52)
bus clock signal that is generated, (III is a sequence circuit that manages the operation of this read-after-write mechanism, and α4 indicates that this read-after-write mechanism is currently using the bus. The bus busy signal, a, is the main memory that this mechanism sends to the system bus.
This is a read command signal.

The read-after-write mechanism (6:) according to the present invention is connected to the highest priority position of the system bus (Sl). It is sufficient to simply connect it to a conventional data processing device.

The data writing operation from the CPU device (1) or the input/output control device (4) to the main memory device (2) is executed according to the timing shown in FIG. The memory address (7) is output from the CPU unit +11 or the input/output control unit (4) to the system bus (51). Next, a memory write command (81) is output, and a data signal is also output. In this embodiment, since data is not involved, FIGS. 1, 2, and 3 are omitted.

In order to start the memory read operation immediately after the memory write, the memory address signal (7) is
Address latch +91K is saved by command signal (8). At the same time, sequence circuit aj is activated to obtain the right to use the system bus (51), and bus clock signal a is activated.
The bus request signal (1G is the system bus (s
i) Sent to. System bus control circuit (52
), the bus response signal αat is returned in response to bus requests in order of priority, and requests from the read-after-write mechanism (6) of the present invention connected to the position with the highest priority are immediately granted. As a result, the right to use the bus immediately after the memory write operation is all set to the read-after-write mechanism (6). Bus response signal α
The sequence circuit that receives D (lj is the bus busy signal I
is established in synchronization with the bus clock signal (Iz). In this state, the right to use the bus is set to the read-after-write mechanism (6).
In this state, the memory read command (15) may be sent to the system bus (51). When the bus busy signal a is established, the sequence circuit αj first sends the memory read command (15) to the system bus (51).
Address signal stored in address latch (9) as address signal (7) (referred to as latched address)
Send out.

After that, send the memory read command a9 to the system bus (
51). The main storage device (memory) (2) executes a memory read operation in response to a memory read command α, and at the same time executes a parity check operation of a parity check generation mechanism (3).

Therefore, if the memory write operation executed just before is defective and a parity error occurs, the error can be discovered immediately. This is an error in the previous write operation.
, when searching for the cause of an error, it is easy to narrow down the 9 conditions.You can expect a significant reduction in the time it takes to resolve a problem.

As described above, in the above embodiment, the read-after-write mechanism (6) is provided with the address latch +97, but the read-after-write mechanism (51) has a mechanism for latching data on the system bus (51) and a read-after-write mechanism. A comparison mechanism may be installed to compare and check the data read as a result of writing.

In addition, if a condition setting mechanism is added so that the conditions to be checked, e.g. write operations only to a specific address area, are checked by the read/book/write mechanism, intervention to the system bus is performed only when checking is necessary. Since the occurrence of this error has no effect at all during normal data processing operations, it is possible to suppress the reduction in data processing throughput to the necessary minimum level and obtain a checking effect.

〔Effect of the invention〕

As described above, according to the present invention, the read-after-write mechanism of the main memory device is configured to be connected without affecting the data processing device at all, so it can be removed and removed freely, and only when an error occurs. It is possible to operate the device by incorporating it and not normally connecting it, which has the effect of making the device cheaper. In addition, read-after-write processing is executed purely as hardware without affecting the software of the data processing device at all, so it is fast and greatly reduces the time required to investigate and solve the cause when wrinkle parity errors occur. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation timing of the embodiment of the present invention. FIG. 3 is a block diagram showing a conventional data processing device. (1) is the CPU device, (2) is the main memory, (3) is the parity check/generate mechanism, (4) is the input/output side 9N&, (sl) is the system bus t (
52) Babasu control device, (6) is a read book
Write mechanism, (7) is main memory (memory) address signal,
(81 is the main memory write command signal, (9
) is the address latch, α is the bus request signal, αD is the bus response signal, α2 is the bus clock signal, αj is the sequence circuit, (141 is the bus busy signal, α9 is the main memory (
Memory) read command signal. In Figure 9, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A data processing device consisting of a main storage device with a parity check function, a CPU device that manages the entire system, an input/output control device that controls input/output devices, and a system bus that has control logic for bus usage rights that connects these devices. , has a function to detect when a write command to the main memory is output to the main memory, and additionally adds a mechanism to automatically read the address immediately after writing by memorizing the written address. A data processing device characterized by making it possible.