JPS5836439B2 - Buffer memory access processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a buffer memory access processing system, particularly a data processing system having a buffer memory that holds a copy of the contents of a main memory, in which an access request source accesses the buffer memory. If an error occurs in the read data when accessed, the main storage device is accessed in the same way as if the data desired by the access requester did not exist in the buffer memory, and the access requestor is a buffer memory that always receives error-free data and prevents the access requester from being involved in buffer memory failures.
This relates to memory access processing methods.

In a data processing system having a buffer memory, a copy of the contents of the main memory is held in the buffer memory, and an access request source can proceed with processing while accessing the buffer memory.

That is, processing is performed based on the data read from the buffer memory.

However, if the desired data does not exist in the buffer memory, the main storage is accessed, one block of information including the desired data is loaded, and the desired data is sent to the access requester. I am trying to pass data.

Generally, a data processing system having a buffer memory is controlled as described above, but if the desired data is present on the buffer memory, an error has occurred in the data read from the buffer memory. Conventionally, this is controlled as follows.

That is, for example, a fault detection circuit section is provided on the buffer memory device side to perform an error check on data read from the buffer memory.

However, conventionally, the error check described above takes time, and the data read from the buffer memory is immediately delivered to the access request source, and the access request source proceeds with processing based on the data.

Under this condition, if it is determined through the error check that an error has occurred, the access request source is notified of this fact.

The access request source learns that there is an error in the data that is already being processed, and has no choice but to cancel the processing.

If the process can be retried, the data read process is retried.

At the time of the retry, a method of accessing the buffer memory again in the same way as above is considered, but in general, taking into consideration that a fixed failure may occur in the buffer memory, the main memory is accessed at the time of the retry. be accessed directly.

That is, desired data is read and received from the main memory.

In this conventional method, if an error occurs in the data read from the buffer memory, the process is often stopped, and even if a retry is possible, the countermeasures are complicated.

The present invention is aimed at solving the above-mentioned problems, and is aimed at allowing the access request source to operate as if it were capable of receiving correct data by accessing the buffer memory.

To this end, the buffer memory access processing method of the present invention includes a main memory device, a buffer memory device that holds a copy of the memory contents of the main memory device, and an access request source, and the buffer memory access processing method of the present invention is provided with a main memory device, a buffer memory device that holds a copy of the memory contents of the main memory device, and an access request source. The address array section and the data section constituting the memory device are accessed substantially in parallel, and when desired data exists on the buffer memory device, the data is read out, and when the data does not exist, the main storage device is accessed. In a data processing system having a buffer memory device which is accessed to read the desired data, a failure detection circuit unit detects an error in data read from the buffer memory, the buffer memory device described above; An address comparison circuit unit detects whether or not desired data exists on the device, and an error detection signal from the failure detection circuit unit and a non-existence signal from the address comparison circuit unit are output at substantially the same timing. The present invention is characterized in that it includes a judgment circuit section that performs OR logic based on the judgment circuit section, and a main memory device access starting circuit section that starts access to the main memory device based on the output signal from the judgment circuit section.

This will be explained below with reference to the drawings. The figure shows the configuration of an embodiment of the present invention.

In the figure, 1 is a buffer memory device, 2 is a main storage device, 3 is an access request source, 3 is an address array section of the buffer memory, 4 is a data section of the buffer memory, 5 is a buffer memory control section, 6 is the main memory access control unit, 7
8 is an address comparison circuit that detects whether desired data exists on the buffer memory, and 8 is a fault detection circuit that detects whether there is an error in the data read from the buffer memory. 9 is a main memory access start circuit, 10, IL12 is an AND circuit, 13.14 is an OR circuit, 15.16 is a gate, R/
W represents a read/write control signal, ADRS represents access address information, and DATA represents data information.

As is conventionally known, the contents stored in the main memory are transferred block by block to the illustrated data section 4 and held there.

An address array section 3 is prepared to indicate the block unit information held in the data section 4, and part of the address information of the block unit information held in the data section 4 is transferred to the address play section 3. is stored within.

When the access request source accesses the buffer memory device 1, the control is performed as follows.

That is, the access request source 3 issues address information ADRS of desired data, and issues a read/write signal R/W to perform read access, for example.

The buffer access control unit 5 learns that it is a read access and enters control.

At this time, read access is performed to the address array section 3 and the data section 4 by the separate section of the address information ADRSO.

From the address array section 3, the address play section 3
Part of the address information stored in (part of the address information of the block unit information stored in the data section 4)
Generally, a plurality of signals are read out and supplied to the address comparison circuit section 7.

A part of the access address information ADRS is directly supplied to the address comparison circuit section 7, and is compared with part of the plurality of read address information.

When a portion of the read address information and a portion of the access address information ADRS are found to match, the address comparison circuit section 7 indicates from which position the read address information ADRS is read. and emits a presence signal F.

During this time, the data section 4 is also being accessed as described above.
Generally, a plurality of pieces of block unit information are read out from the data section 4 as well.

In the case of the conventional method, it is determined that the block unit information corresponding to the position where the presence signal F is issued is desired, and
The selected data is delivered to the access request source 3 via the illustrated OR circuit 14.

In the case of the present invention, the data read from the data section 4 as described above is supplied to the failure detection circuit section 8, where an error check is performed.

If there is no error, i.e. the indicated signal *ER is logical
1'' and the presence signal F is issued as described above, the AND circuit 12 outputs a logic ``1'', and the data selected by the gate 15 is output to the OR circuit 14 as in the conventional method. is passed to the access requester via.

As a result of the comparison process by the address comparison circuit section 7, if there is no match among all of the plurality of pieces of information read out from the address array section 3, the address comparison circuit section 7 issues a non-existence signal NF. .

Therefore, in both the conventional method and the method of the present invention,
None of the block unit information read from the data section 4 is delivered to the access request source.

When the non-existence signal NF is issued, the illustrated AND circuit 1
0 is turned on, a read/write signal R/W is supplied to the illustrated memory access control unit 6, and the main storage device 2
Access to is started.

That is, the memory access control unit 6 instructs the main storage device 2 to load a block in a well-known manner, and the access address information ADRS issued by the access request source is validated on the main storage device 2 side.

As a result, one block of information including the address designated by the access address information ADRS is read from the main memory device 2.

The memory access control section 6 turns on the gate 16 and writes to the data section 4.

During this writing, the desired data in the block-loaded block unit information is delivered to the access request source via the OR circuit 14.

Note that the block-by-block information that has been loaded above is error-checked on the main storage device 2 side.
The data is guaranteed to be correct.

Further, when writing the block-loaded block unit information to the data section 4, a replacement process is performed in the buffer memory device 1 as is well known, but a detailed explanation thereof will be omitted.

In the case of the present invention, when the non-existence signal NF is issued by the address comparison circuit section 7, the main memory device 2 is accessed as described above, and the data block-loaded from the main memory device 2 is sent to the access request source. It goes without saying that the address comparison circuit section 7 issues the presence signal F, but if there is an error in the data read from the data section 4, the data is automatically transferred to the main memory device 2 in the same manner as above. be accessed.

That is, in the case of the present invention, when the access request source makes an access, the data section 4 is accessed together with the address array section 3 as described above.

In parallel with the address comparison performed by the address comparison circuit section 7, an error check is performed on the data read from the data section 4 by the failure detection circuit section 8 using high-speed logic elements.

If an error has occurred, even if the address comparison circuit unit 7 issues the presence signal F, the AND circuit 12 is not turned on, but the AND circuit 11 is turned on.

As a result, the AND circuit 10 is turned on via the OR circuit 13, a read/write signal is supplied to the memory access control section 6, and the main storage device 2 is accessed.

That is, in the same way as when the address comparison circuit section 7 issues the non-existence signal NF, the data read from the main memory device 2 is also delivered to the access request source.

In other words, the access requester will always receive correct data without errors in response to the access it has issued.

Therefore, the access request source is not involved in the buffer memory failure at all, and is freed from backup processing for the buffer memory failure.

Note that when the main storage device 2 is accessed based on the error signal ER issued by the failure detection circuit section 8, the block unit information that has been loaded in the main storage device 2 is also blocked by the error in the data section 4. It can be assumed that it is stored in the location where it existed.

By doing so, even if a temporary failure occurs in the buffer memory 4, it is possible to correct it correctly.

As explained above, according to the present invention, the data received by the access request source is correct data, and there is no need for the access request source to take measures when an error occurs in the data read from the buffer memory. Become.

In the above description, the access request source receives the data after the AND circuit 12 is turned on, but the present invention can adopt a method of receiving the data before error checking as in the conventional method. .

In this case, the access request source will need some backup processing when an error occurs, but the buffer memory device 1 will autonomously access the main storage device 2, and the access request source will be correct. Data can be received, and backup processing is simplified compared to the conventional case where the access request source accesses the main storage device through retry processing.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 is a buffer memory device, 2 is a main memory device, 3 is an access request source, 3 is an address array section, 4 is a data section, 5 is a buffer memory control section, 6 is a main memory access control section, Reference numeral 7 represents an address comparison circuit section, 8 a failure detection circuit section, and 9 a main memory access start circuit section.

Claims (1)

[Scope of Claims] 1. A main storage device, a buffer memory device that holds a copy of the storage contents of the main storage device, and an access request source, and when processing progresses, addresses and The array section and the data section are accessed substantially in parallel, and if desired data exists on the buffer memory device, the data is read out, and if the data does not exist, the main storage device is accessed and the desired data is read. In a data processing system having a buffer memory device configured to output data from the buffer memory, a failure detection circuit unit detecting an error in data read from the buffer memory;
An address comparison circuit unit detects whether or not desired data exists on the memory device, and an error detection signal from the failure detection circuit unit and a non-existence signal from the address comparison circuit unit are output at substantially the same timing. The buffer is characterized in that it has a judgment circuit section which determines the OR logic based on the judgment circuit section, and a main memory device access starting circuit section which starts access to the main memory device based on the output signal from the judgment circuit section. Memory access processing method. 2. A patent claim characterized in that the access request source accesses the buffer memory device and receives read data read from the buffer memory device and error-checked by the fault detection circuit. The buffer memory access processing method described in item 1.