JPH08328997A - Local bus access method and bus adapter - Google Patents

Abstract

(57) [Summary] [Purpose] Without locking the local bus by a program,
A method for accessing a local bus space from a module on the main bus and a bus adapter are provided. [Configuration] In a bus adapter 4, address / data information is held in a program writable register 41/42, and an access control unit 40 accesses a local bus 5 independently of a main bus 3. By referring to the busy flag 50, the program can confirm the completion of the local bus access by the access control unit 40. The fault processing unit 51 detects a fault due to an error in the program procedure or a failure of the module on the local bus, and performs processing such as reporting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a system having a main bus to which a CPU or the like is connected and a local bus to which a module for performing DMA is connected, and more particularly to a system such as a CPU or the like on the main bus. The present invention relates to a method of accessing a local bus from a module and an improvement of a bus adapter that connects a main bus and a local bus.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS.

FIG. 9 is a schematic block diagram showing an example of a system having a local bus to which a module for performing DMA is connected. In FIG. 9, reference numeral 3 is a main bus, and modules such as a CPU 1 and a main memory 2 are connected to the main bus. Reference numeral 5 denotes a local bus on which modules 6a and 6b for performing DMA are connected. Reference numeral 4a is a bus adapter for connecting the main bus 3 and the local bus 5.
The bus adapter 4a includes a local bus arbitration unit 4b, and the local bus arbitration unit 4b includes a lock state display flag 4c.

FIG. 10 is a flowchart showing a conventional procedure for the CPU 1 to access the local bus space. Here, a case where the CPU 1 accesses the register 7 in the module 6a on the local bus 5 will be described as an example.

First, the CPU 1 issues a local bus lock instruction to the bus adapter 4a (step 500 in FIG. 10). Bus adapter 4a that received this lock instruction
Then, the local bus arbitration unit 4b changes the modules 6a, 6
local bus 5 by suspending DMA permission to b
Is locked (step 600 in FIG. 10), and the lock state display flag 4c is set to "1" to indicate that the lock state is set (step 601 in FIG. 10).

After the CPU 1 reads the lock state display flag 4c and confirms the lock of the local bus 5 (see FIG. 1).
0, step 501), the local bus 5 is directly accessed via the bus adapter 4a to access the register 7 in the module 6a (FIG. 10, steps 502 and 602).

After this access is completed, the CPU 1 issues an instruction to unlock the local bus 5 to the bus adapter 4a (FIG. 10, step 503). In the bus adapter 4a which has received the release instruction, the local bus arbitration unit 4b releases the lock of the local bus 5 (FIG. 10, step 60).
3), the lock state display flag 4c is set to "0" to display that the lock state is not set (FIG. 10, step 60).
4).

[0008]

As described above, conventionally, when accessing the local bus space from a module such as a CPU on the main bus, a method of locking the local bus by a program has been adopted. In other words, the conventional bus adapter has a configuration based on such an access method.

However, in the method of locking the local bus when accessing the local bus space, when the unlocking of the local bus is delayed due to interrupt processing or the like, the DMA permission of the module on the local bus is held for a long time. ,
There was a problem that failures such as overrun and underrun occurred.

The object of the present invention is to solve the problems associated with such local bus access.

[0011]

To achieve the above object, according to the present invention, an improved method for accessing a local bus space from a module on a main bus and an improvement for implementing this method. Bus adapter is provided.

The outline of the local bus access method of the present invention is as follows. First, in the reading of the local bus space by the module on the main bus, a step of setting a read address from the module to a control device provided between the main bus and the local bus, and the control device Independently of the bus, perform a read access to the local bus space according to the read address and hold the read data; a step of issuing a read request from the module to the control device; and a step of responding to the read request. The controller outputs the held read data to the main bus and the module takes in the read data, and the writing of the local bus space by the module on the main bus is performed by the module. Set the write address and write data in the control device provided between the main bus and the local bus And the step of performing a write access of the local bus space for writing the write data according to the write address independently of the main bus in the control device. That is, the program is performed without locking the local bus.

The bus adapter according to the present invention can be used as a control device for the method of the present invention.
First, the characteristic of the configuration related to the reading of the local bus space is that an address holding unit that can set an address for reading the local bus space from a module on the main bus, a data holding unit, and an address in the address holding unit. Is set, the read access of the local bus space is performed independently of the main bus according to the address set in the address holding unit, the read data is held in the data holding unit, and thereafter, on the main bus. In response to a read request for the local bus space from this module, the controller outputs the read data held in the data holding unit to the main bus, and the controller is executing access to the local bus space. And a flag which indicates whether or not the module on the main bus can refer. Further, the characteristic of the configuration related to the writing of the local bus space is that an address holding unit and a data holding unit capable of setting an address and data for writing from the module on the main bus to the local bus space, respectively, and the address holding unit. For writing the data set in the data holding unit, independently of the main bus, according to the address set in the address holding unit when the address and the data are set in the unit and the data holding unit, respectively. It has a control unit for performing a write access to the local bus space, and a flag which can be referred to from a module on the main bus and which indicates whether or not the control unit is executing an access to the local bus space. . Another structural feature of the bus adapter of the present invention is that the controller has means for handling failures associated with accessing the local bus space.

[0014]

According to the above-described method of the present invention, the module on the main bus reads or writes the local bus space without locking the local bus by the program. It is possible to shorten the time that the above module holds the DMA and avoid the occurrence of failures such as overrun and underrun.

According to the bus adapter of the present invention, the method of the present invention can be easily realized. That is,
When the bus adapter of the present invention is used as the control device of the method of the present invention, the module on the main bus sets the read address in the address holding unit of the bus adapter, and the completion of the read access of the local bus space by the bus adapter is confirmed by the bus adapter. After confirming by referring to the flag, by issuing a read request to the bus adapter, the local bus space can be read without locking the local bus by the program. The module on the main bus confirms that the bus adapter is not accessing the local bus space by referring to the flag of the bus adapter, and then writes the write address and write data to the address holding unit and the data holding unit of the bus adapter. By setting to, it is possible to write to the local bus space without locking the local bus by the program.

Further, since the bus adapter of the present invention has means for handling a failure related to access to the local bus space, malfunction of the bus adapter or reading of erroneous data due to an error in the program procedure is avoided, or The reliability of the system can be improved by detecting the failure due to the failure of the module on the local bus.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the same or corresponding parts as in FIG. 9 are designated by the same reference numerals.

In FIG. 1, 1 is a CPU, 2 is a main memory, 3 is a main bus, and 5 is a local bus. 6a and 6b are D connected to the local bus 5.
This is a module that performs MA.

A bus adapter 4 connects the main bus 3 and the local bus 5, and has an access control unit 40, an address register 41, a data register 42 and a local bus arbitration unit 43 inside.

The access control section 40 is a unit for controlling access to the main bus 3 and the local bus 5,
It has a function of controlling the address register 41 and the data register 42 to read or write the local bus space independently of the main bus 3, and a function of responding the contents of the data register 42 to the read of the local bus space. The access control unit 40 further includes the busy flag 50.
And a failure processing unit 51.

The busy flag 50 is used by the access control unit 40.
Is a flag that is set to "1" during access to the local bus and set to "0" when the access is completed.
It can be referenced from PU1.

The failure processing unit 51 has a role of processing a failure associated with access to the local bus space. For example, during the access operation of the local bus space, the CPU 1
A function to monitor whether the access to the local bus space and the access to the address register 41 from the
It has a function of comparing the read address output from the CPU 1 with the contents of the address register 42, a function of monitoring the execution time of the access operation of the local bus 5, and the like, which will be described in detail later.

The address register 41 is a register for holding an access address to the local bus space. The read address is set by the CPU 1 at the time of reading, and the write address output from the CPU 1 at the time of writing is the hardware of the bus adapter 4. Stored by operation.

The data register 42 stores the read data output from the modules 6a and 6b on the local bus 5 at the time of reading and the write data output from the CPU 1 at the time of writing by the hardware operation of the bus adapter 4, respectively. Is.

The local bus arbitration unit 43 is a unit for arbitrating the right to use the local bus 5.

Reference numerals 60 to 65 are interface signals of the main bus 3. 60 is a read request signal (MRD), 61
Is a write request signal (MWT), 62 is a read / write response signal (MACK), and 63 is an address signal (MAD).
R), 64 is a data signal (MDATA), and 65 is a CPU
1 is a failure report signal (MERR).

Reference numerals 70 to 74 are interface signals of the local bus 5. 70 is a read request signal (LRD), 7
1 is a write request signal (LWT), 72 is a read / write response signal (LACK), 73 is a local address signal (LADR), and 74 is a local data signal (LDAT).
A).

Reference numeral 80 denotes a main bus output instruction signal, which controls the output of the data register 42 to the main bus 3.
Reference numeral 81 represents an address latch signal, which is read by the CPU 1
To fetch the read address set value output to MDATA 64, and to write the write address output to MADR 63 from CPU 1 at the time of writing. Reference numeral 82 denotes a data latch signal, which is used for fetching read data output by the local bus modules 6a and 6b onto the LDATA 74 when reading, and for the CPU 1 when writing.
Respectively instruct to fetch the write data output on the MDATA 64. Reference numeral 83 is a local bus address output instruction signal, which controls the output of the address register 41 to the local bus 5. Reference numeral 84 is a local bus data output instruction signal, which is a data register 4 for the local bus
2 output control.

The triangular symbol inside the bus adapter 4 is
Although it is a signal input / output buffer gate, it is not provided with a reference numeral because it does not complicate the drawing and the description.

Next, the read / write operation from the CPU 1 to the local bus space will be described with reference to the block diagram of FIG. 1, the time charts of FIGS. 2 to 6 and the flow charts of FIGS.

First, the read operation of the local bus space by the CPU 1 will be described. FIG. 7 is a flowchart of the read operation, and FIGS. 2 to 4 are time charts related to the read operation.

First, the CPU 1 writes the address of the local bus space to be read in the address register 41 (FIG. 7, step 100). At this time, the MADR 6 is transferred from the CPU 1 to the bus adapter 4 at the timing shown in FIG.
3, MDATA 64, and MWT 61 are output.

The access control unit 40 receiving these signals stores the read address value on the MDATA 64 by the address latch signal 81 (FIG. 7, step 20).
0) and the busy flag 50 is set to "1" (step 201 in FIG. 7). MACK6 for CPU1
In response to 2, the write to the address register 41 is completed. At the same time, reading of the local bus is started.

The access control unit 40 first requests the bus right of the local bus 5 to the local bus arbitration unit 43 and acquires the bus right (FIG. 7, step 202). Then, at the timing shown in FIG. 3, the LADR 73 and the LRD 70 are output to issue a read request for the local bus 5. By turning on the local bus address output signal 83, the contents of the address register 41 are output to the LADR 73.

Upon receiving the response signal LACK 72 for this request, the access control unit 40 receives the data latch signal 82.
Is turned on to read the read data from the LDATA 74 (step 203 in FIG. 7). Then, the local bus arbitration unit 43 is notified of the release of the bus right (FIG. 7, step 20).
At the same time, the busy flag 50 is set to "0" (step 205 in FIG. 7).

On the other hand, the CPU 1 polls the busy flag 50, and when the flag becomes "0" (FIG. 7,
In step 101), the local bus space is read (step 102 in FIG. 7).

The busy flag 50 becomes "0", and the CPU
When the reading of the local bus space 1 is started, the CPU
1 to the bus adapter 4 at the timing shown in FIG.
ADR63 and MRD61 are output.

Upon receiving these signals, the access control section 40 turns on the data output instruction signal 80 to turn on the data line M.
The contents of the data register 43 are output to DATA64, and C
A response signal MACK62 is responded to PU1 (FIG. 7, step 206).

CPU 1 sends MDATA by MACK 62
The data on 64 is taken in, and the read operation is completed.

Here, if the response signal LACK 72 does not turn on in step 203 of FIG. 7 even after a certain period of time, it is expected that the module (6a, 6b) on the local bus 5 will fail, and therefore the access control unit 40 will not operate locally. The access to the bus 5 is stopped, and the MERR 65 is turned on to report a failure to the CPU 1. The fault processing unit 51 performs the fault detection and the report instruction due to the time excess.

Further, the failure of the hardware malfunction due to the error of the program procedure is also avoided. That is, FIG.
When another access to the local bus space arrives from the CPU 1 during steps 201 to 205, that is, when the busy flag 50 is “1”, the failure processing unit 51 determines that there is a failure and issues a report instruction, and responds to this. Then, the access control unit 40 turns on the MER 65 and reports a failure to the CPU. Similarly, even if the busy flag 50 is "1", when the read address is set again from the CPU 1 to the address register 41, the failure processing unit 51 determines that there is a failure, issues a report instruction, and responds to this by accessing. The control unit 40 turns on the MERR 65 to report a failure to the CPU 1, and protects the contents of the address register 41 by suppressing the output of the address latch signal 81. Also, the MA output by the CPU 1 in step 102 of FIG.
When the value of the DR 63 and the value of the address register 41 do not match, the address control unit 40 turns on the MER 65 and sets the CP
Report a failure to U1. The fault processing unit 51 also detects a fault by the address comparison and gives a report instruction.

Next, the write operation of the local bus space by the CPU 1 will be described. FIG. 8 is a flowchart of the write operation, and FIGS. 5 and 6 are time charts related to the read operation.

First, the CPU 1 reads the busy flag 50 and confirms whether it is "0" (FIG. 8, step 30).
0). When the flag is "1", polling is performed until "0" can be read.

If the busy flag 50 is "0", CP
U1 executes a write to the local bus space (Fig. 8,
Step 301). When writing to the local bus space, C
MADR 63, MDATA 64, and MWT 61 are output from the PU 1 to the bus adapter 4 at the timings shown in FIG.

Upon receiving these signals, the access control section 40 receives the write address on the MADR 64 with the address latch signal 81 and the MDAT with the data latch signal 82.
The write data on A65 is stored in the address register 41 and the data register 42, respectively (FIG. 8, step 401). Further, the busy flag 50 is set to "1" (step 402 in FIG. 8). MACK for CPU1
In response to 62, the write operation is completed (actual access is not completed). Then, writing to the actual local bus space is started.

First, the bus right of the local bus 5 is requested to the local bus arbitration unit 43 and the bus right is acquired (step 403 in FIG. 8). Then, at the timing shown in FIG.
It outputs DR73, LDATA74, and LWT71 to make a write request. Local bus address output signal 83
Is turned on, the contents of the address register 42 are LAD
By outputting to R73 and turning on the local bus data output signal 84, the contents of the data register 43 are transferred to LDATA7.
4 is output.

Upon receiving the response signal LACK 72 for this request, the access control unit 40 completes the actual write operation (FIG. 8, step 404) and notifies the local bus arbitration unit 43 of the release of the bus right (FIG. 8, FIG. Step 405),
The busy flag 50 is set to "0" (step 40 in FIG. 8).
6).

Here, the access control section 40 cooperates with the failure processing section 51 to perform the same failure processing as in the read operation. That is, during steps 402 to 405 of FIG. 8, that is, during the busy flag 50 is "1", the CPU
When another access of the local bus space comes from 1, ME
The RR 65 is turned on to report a failure to the CPU 1. If the response signal LACK 72 does not turn on even after a certain period of time in step 404 of FIG. 8, the access control unit 40
Cancels access to local bus 5 and
Turn on 65 to report a failure to CPU 1.

Thus, in the bus adapter 40,
In response to the read request from the CPU 1, the previously read data is responded to, the address and the data are once held in response to the write request, and writing to the local bus space is performed independently of the CPU 1, whereby the CPU 1 DMA
It is possible to access the local bus space without locking the local bus 5 to which the modules 6a and 6b for performing the operation are connected. Therefore, it is possible to avoid overrun / underrun caused by a long DMA hold time of the module on the local bus. Also,
The system reliability can be improved by having a function of handling a failure due to an error in the programming procedure or a failure of the module on the local bus 5.

In this embodiment, the address register, the data register and the busy flag are shared by the read operation and the write operation, but it goes without saying that separate read and write operations may be provided.

[0052]

As described above in detail, according to the local bus access method of the present invention, there is a problem in the case where a module on the main bus reads and writes to the local bus space, that is, on the local bus. It is possible to solve the problem of the increase in the DMA holding time of the module and the problem of occurrence of troubles such as overrun and underrun. Further, according to the bus adapter of the present invention, it is possible to easily access the local bus space by the local bus access method of the present invention, and it is possible to prevent an error due to an error in a program procedure or a failure of a module on the local bus. There is an effect that it can be processed appropriately and the reliability of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a CP on a main bus according to an embodiment of the present invention.
6 is a time chart for explaining an operation of reading a local bus space from U.

FIG. 3 is a CP on a main bus in one embodiment of the present invention.
6 is a time chart for explaining an operation of reading a local bus space from U.

FIG. 4 is a CP on a main bus according to an embodiment of the present invention.
6 is a time chart for explaining an operation of reading a local bus space from U.

FIG. 5 is a CP on a main bus in one embodiment of the present invention.
7 is a time chart for explaining an operation of writing from U to a local bus space.

FIG. 6 is a CP on a main bus in one embodiment of the present invention.
7 is a time chart for explaining an operation of writing from U to a local bus space.

FIG. 7 is a CP on a main bus according to an embodiment of the present invention.
7 is a flowchart showing a flow of an operation of reading a local bus space from U.

FIG. 8 is a CP on a main bus in one embodiment of the present invention.
It is a flowchart which shows the flow of operation which writes from U to the local bus space.

FIG. 9 is a block diagram for explaining a conventional technique.

FIG. 10 is a flowchart for explaining a conventional technique.

[Explanation of symbols]

 1 CPU 2 Main memory 3 Main bus 4 Bus adapter 5 Local bus 6a, 6b Module on local bus 40 Access control unit 41 Address register 42 Data register 43 Local bus arbitration unit 50 Busy flag 51 Fault processing unit 60 Read request signal (MRD) 61 write request signal (MWT) 62 read / write response signal (MACK) 63 address signal (MADR) 64 data signal (MDATA) 65 failure report signal (MERR) 70 read request signal (LRD) 71 write request signal (LWT) 72 Read / write response signal (LACK) 73 Local address signal (LADR) 74 Local data signal (LDATA) 80 Main bus output instruction signal 81 Address latch signal 82 Data latch signal 83 Local Scan address output instruction signal 84 local bus data output instruction signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Ishii 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Hitachi Works Office Systems Division (72) Inventor Yoichi Tanaka 810 Shimoimazumi, Ebina City, Kanagawa Hitachi Works Office System Division (72) Inventor Satoshi Fukawa 1 Horiyamashita, Hadano City, Kanagawa Prefecture

Claims (7)

[Claims] 1. A step of setting a read address for reading a local bus space from a module on a main bus to a control device provided between the main bus and the local bus; Independently of the main bus, read access of the local bus space is performed according to the read address, the read data is held, the read request is issued from the module to the control device, and the read request is responded. The controller outputs the read data held therein to the main bus, and the module fetches the read data, and the module on the main bus locks the local bus by a program. A local bus access method characterized in that the local bus space is read without performing. 2. A step of setting write data and a write address for writing from a module on the main bus to a local bus space in a control device provided between the main bus and the local bus, and the control device. Independently of the main bus, according to the write address, write access of the local bus space for writing the write data is performed, and a module on the main bus uses the program to access the local bus. A local bus access method characterized by writing the local bus space without locking. 3. A bus adapter for connecting a main bus and a local bus, wherein an address holding unit capable of setting an address for reading a local bus space from a module on the main bus; a data holding unit; When an address is set in the address holding unit, read access to the local bus space is performed according to the address set in the address holding unit independently of the main bus, and read data is held in the data holding unit. A control unit for outputting the read data held in the data holding unit to the main bus in response to a read request for the local bus space from a module on the main bus; and the control unit accessing the local bus space. Display whether or not is running,
A bus adapter having a flag that can be referenced from a module on the main bus. 4. A bus adapter for connecting a main bus and a local bus, wherein an address holding unit and a data holding unit capable of setting an address and data for writing from a module on the main bus to a local bus space, respectively. And, when an address and data are set in the address holding unit and the data holding unit, respectively, the data set in the data holding unit is set independently of the main bus according to the address set in the address holding unit. And a flag referable from the module on the main bus, which indicates whether or not the control unit performs write access to the local bus space for writing, and whether or not the control unit is executing access to the local bus space. A bus adapter having: 5. The bus adapter according to claim 3 or 4, wherein the control unit has means for handling a fault related to access to the local bus space. 6. The local bus access method according to claim 1, wherein the control device is the bus adapter according to claim 3, and the module on the main bus reads the read address when reading the local bus space. It is set in the address holding unit of the bus adapter, and after confirming that the read access of the local bus space by the bus adapter is completed by referring to the flag of the bus adapter, the read request is issued to the bus adapter. A local bus access method characterized in that 7. The local bus access method according to claim 2, wherein the control device is the bus adapter according to claim 4, and when the module on the main bus writes the local bus space, the bus adapter is After confirming that the local bus space is not being accessed by referring to the flag of the bus adapter, a write address and write data are set in the address holding unit and the data holding unit of the bus adapter, respectively. How to access the local bus.