JPS6123348A - Resin sealing type semiconductor device - Google Patents
Resin sealing type semiconductor deviceInfo
- Publication number
- JPS6123348A JPS6123348A JP59144683A JP14468384A JPS6123348A JP S6123348 A JPS6123348 A JP S6123348A JP 59144683 A JP59144683 A JP 59144683A JP 14468384 A JP14468384 A JP 14468384A JP S6123348 A JPS6123348 A JP S6123348A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- die
- bonded portion
- die attach
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、樹脂モールドされてなる半導体素子用プラス
チックパッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a plastic package for semiconductor elements which is molded with resin.
（従来技術）
従来の樹脂をもってモールドされてなるプラスチックパ
ッケージに於いては、リードフレームの所定部に金■ロ
ー材あるいは接着剤を用いて素子を接着し、電極結線後
樹脂モールドした型になっている。この場合素子を乗せ
たダイアタッチ部の反対側の面は、同等表面処理が施さ
れていない。(Prior art) In conventional plastic packages molded with resin, the elements are bonded to predetermined parts of the lead frame using gold brazing material or adhesive, and after electrodes are connected, the package is molded with resin. There is. In this case, the surface opposite to the die attach portion on which the element is mounted is not subjected to equivalent surface treatment.
近年集積回路素子の薄肉化が進んで来ている。In recent years, integrated circuit elements have become thinner.
この場合、従来のリードフレームでは、ダイアタッチ部
の反対側の面からモールド樹脂表面までの距離が短かく
なる。その時、本発明者の実験によればその部分でとく
にモールド樹脂のクラックが入りおすいことがわかった
。これはリードフレーム材の膨張率と樹脂の膨張率とが
違っている為、樹脂厚が薄くなればなるほどクラックが
入りやすくなると考えられる。そ七て、このクラックは
とくに樹脂厚の薄い部分、即ち上記の部分に生じやすい
。In this case, in the conventional lead frame, the distance from the surface opposite the die attach portion to the surface of the molding resin is shortened. At that time, according to experiments conducted by the present inventor, it was found that cracks in the mold resin were particularly likely to occur in that area. This is because the expansion coefficient of the lead frame material and the expansion coefficient of the resin are different, and it is thought that the thinner the resin, the more likely cracks will occur. Seventh, these cracks are particularly likely to occur in areas where the resin is thin, ie, in the above-mentioned areas.
（発明の目的）
本発明はかかる不具合を改善したパッ□ケージを提供す
ることである。(Object of the Invention) The present invention is to provide a package in which such defects are improved.
（発明の構成）
本発明は、リードフレーム材と樹脂との接着性が良い事
がかえって樹脂に応力の集中を起こして、クラック発生
を助長しているとの知見に基き、ダイアタッチ部の反対
側の面に樹脂と密着しにくい物質を設けたことを特徴と
する。(Structure of the Invention) The present invention is based on the knowledge that the good adhesion between the lead frame material and the resin actually causes stress concentration on the resin and promotes the occurrence of cracks. It is characterized by having a material on the side surface that does not easily adhere to resin.
こうする事によりリードフレーム材と樹脂の膨張率差は
、ダイレクトにはダイアタッチ部下の樹脂には伝わらず
、その影響は緩和され樹脂へのクラックは防止される。By doing this, the difference in expansion coefficient between the lead frame material and the resin will not be directly transmitted to the resin below the die attach, its influence will be alleviated, and cracks in the resin will be prevented.
（実施例の説明） 以下本発明の一実施例を図面を用いて説明する。(Explanation of Examples) An embodiment of the present invention will be described below with reference to the drawings.
第１図は従来のプラスチックパッケージを示す図である
。FIG. 1 is a diagram showing a conventional plastic package.
リードフレーム１のダイアタッチ部２の上に金属ロー材
又は銀ペースト等の接着剤３により半導体素子４を接着
し、ボンディングワイヤ５で該素子の電極とリードフレ
ーム先端にボンディング出来る様に例えば銀メッキした
部分６とを結線し、その後樹脂７でモールドし、最後に
外部リードに例えば錫メッキ８を施したものである。A semiconductor element 4 is bonded onto the die attach part 2 of the lead frame 1 with an adhesive 3 such as a metal brazing material or silver paste, and plated with silver, for example, so that the electrode of the element can be bonded to the tip of the lead frame with a bonding wire 5. After that, the external leads are molded with resin 7, and finally the external leads are plated with tin, for example.
この様な従来のプラスチックパッケージの場合モールド
樹脂７の厚さを薄くしていた時、ダイアタッチ部２下の
樹脂厚が極端に薄くなってくる。In the case of such a conventional plastic package, when the thickness of the mold resin 7 is made thinner, the resin thickness under the die attach portion 2 becomes extremely thin.
リードフレーム素材としては、一般的に４２％Ｎｉ−Ｆ
ｅ 合金が使用されており、樹脂よりも膨張率が小さく
かなりの膨張差が生ずる。又他のリードフレーム素材に
於いても大なり小なり膨張差に存在する。The lead frame material is generally 42% Ni-F.
e alloy is used, and its expansion coefficient is lower than that of resin, resulting in a considerable expansion difference. Also, there are differences in expansion to a greater or lesser extent in other lead frame materials.
リードフレーム素材とモールド樹脂との密着性はリード
フレームとモールド樹脂界面からの水分侵入を防止する
上からも当然良くなければならない。しかし、ダイアタ
ッチ部２の下面の状態を考察してみると、リードフレー
ム素材とモールド樹脂が密着している事から熱膨張衝撃
に対してその膨張差による熱応力ひずみはダイアタッチ
部下面の端部に集中する事となりモールド樹脂７にクラ
ック９が発生する事が認められた。Adhesion between the lead frame material and the mold resin must naturally be good in order to prevent moisture from entering from the interface between the lead frame and the mold resin. However, when considering the condition of the lower surface of the die attach part 2, it is found that because the lead frame material and mold resin are in close contact, thermal stress and strain due to the difference in expansion due to thermal expansion impact will be applied to the lower surface of the die attach part 2. It was observed that cracks 9 were generated in the mold resin 7 as a result.
これに対して第２図は本発明による一実施例を示す図で
ある。On the other hand, FIG. 2 is a diagram showing an embodiment according to the present invention.
本実施例はリードフレーム１のダイアタッチ部２の上に
金属ロー材又は銀ペースト等の接着剤３により半導体素
子４を接着し、ボンディングワイヤ５で該素子の電極と
リードフレーム先端にボンディング出来る様例えば銀メ
ッキした部分６とを結線しである。ここで従来の構造と
異なる点は、ダイアタッチ部２０反対側の面に限定的に
モールド樹脂７と密着しにくい物質例えばフッ素樹脂１
０をコーティングした事である。更に樹脂７でモールド
し、最後に外部リードに例えば錫メッキ８を施す。In this embodiment, a semiconductor element 4 is bonded onto the die attach part 2 of a lead frame 1 using an adhesive 3 such as a metal brazing material or silver paste, and bonding can be made to the electrode of the element and the tip of the lead frame using a bonding wire 5. For example, it is connected to the silver-plated portion 6. Here, the difference from the conventional structure is that a material, such as fluororesin, which is difficult to adhere to the mold resin 7 is limited to the surface opposite to the die attach part 20.
0 coating. Furthermore, it is molded with resin 7, and finally the external leads are plated with tin, for example.
（発明の効果）
この様に本発明の実施例では、ダイアタッチ部２０反対
側の面にフッ素樹脂１０をコーティングしであるので、
リード素材とモールド樹脂７はその部分では密着してお
らず、このため熱膨張衝撃に対してその膨張差による応
力ひずみはダイアタッチ部下面の端部に集中する事がな
くなりモールド樹脂７にクラックの発生はなくなった。(Effects of the Invention) As described above, in the embodiment of the present invention, since the surface opposite to the die attach portion 20 is coated with the fluororesin 10,
The lead material and the mold resin 7 are not in close contact with each other at that part, so the stress strain caused by the difference in expansion due to the thermal expansion impact will not be concentrated at the end of the lower surface of the die attach, and the mold resin 7 will be cracked. The outbreak has stopped.
以上本発明の一実施例を図面により説明したが、本発明
を使用する事によりモールド樹脂厚を薄くしても充分信
頼性の高いプラスチックパッケージとして利用出来る様
になった。One embodiment of the present invention has been described above with reference to the drawings, and by using the present invention, it has become possible to use the plastic package as a sufficiently reliable plastic package even if the thickness of the molding resin is reduced.
＝５−=5-
第１図は従来のプラスチックパッケージを示す断面図で
ある。第２図は本発明の一実施例であるプラスチックパ
ッケージを示す断面図である。
１・・・・・・リードフレーム、５・・・・・・ボンデ
ィングワイヤ、９・・・・・・クラック、２・・・・・
・ダイアタッチ部、６・・・・・・銀メツキ部、１０・
・・・・・フッ素樹脂、３・・・・・・金属ロー材又は
銀ペースト、７・・・・・・モールド樹脂、４・・・・
・・半導体素子、８・・・・・・錫メッキ。FIG. 1 is a sectional view showing a conventional plastic package. FIG. 2 is a sectional view showing a plastic package that is an embodiment of the present invention. 1... Lead frame, 5... Bonding wire, 9... Crack, 2...
・Die attach part, 6...Silver plating part, 10・
...Fluororesin, 3...Metal brazing material or silver paste, 7...Mold resin, 4...
...Semiconductor element, 8...Tin plating.
Claims (1)
てなるプラスチックパッケージに於いて、該素子を支持
するダイアタッチ部の反対側の面に該モールド樹脂と密
着しにくい物質をコーティングした事を特徴とする樹脂
封止型半導体装置。A resin characterized in that, in a plastic package in which a semiconductor element on a lead frame is molded with resin, the surface opposite to the die attach part that supports the element is coated with a substance that does not easily adhere to the molding resin. Sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59144683A JPS6123348A (en) | 1984-07-12 | 1984-07-12 | Resin sealing type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59144683A JPS6123348A (en) | 1984-07-12 | 1984-07-12 | Resin sealing type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123348A true JPS6123348A (en) | 1986-01-31 |
Family
ID=15367826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59144683A Pending JPS6123348A (en) | 1984-07-12 | 1984-07-12 | Resin sealing type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123348A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6370548A (en) * | 1986-09-12 | 1988-03-30 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
| JPS63142855U (en) * | 1987-03-11 | 1988-09-20 | ||
| US4777520A (en) * | 1986-03-27 | 1988-10-11 | Oki Electric Industry Co. Ltd. | Heat-resistant plastic semiconductor device |
| EP0504634A2 (en) * | 1991-03-08 | 1992-09-23 | Japan Gore-Tex, Inc. | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| WO2003044858A3 (en) * | 2001-11-23 | 2004-02-05 | Koninkl Philips Electronics Nv | Semiconductor device and method of enveloping an integrated circuit |
-
1984
- 1984-07-12 JP JP59144683A patent/JPS6123348A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4777520A (en) * | 1986-03-27 | 1988-10-11 | Oki Electric Industry Co. Ltd. | Heat-resistant plastic semiconductor device |
| JPS6370548A (en) * | 1986-09-12 | 1988-03-30 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
| JPH0545063B2 (en) * | 1986-09-12 | 1993-07-08 | Mitsubishi Electric Corp | |
| JPS63142855U (en) * | 1987-03-11 | 1988-09-20 | ||
| JPH0526760Y2 (en) * | 1987-03-11 | 1993-07-07 | ||
| EP0504634A2 (en) * | 1991-03-08 | 1992-09-23 | Japan Gore-Tex, Inc. | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| EP0504634A3 (en) * | 1991-03-08 | 1994-06-01 | Japan Gore Tex Inc | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| US5446315A (en) * | 1991-03-08 | 1995-08-29 | Japan Gore-Tex, Inc. | Resin-sealed semiconductor device containing porous fluorocarbon resin |
| WO2003044858A3 (en) * | 2001-11-23 | 2004-02-05 | Koninkl Philips Electronics Nv | Semiconductor device and method of enveloping an integrated circuit |
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