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JPS63142855U - - Google Patents

Info

Publication number
JPS63142855U
JPS63142855U JP1987036375U JP3637587U JPS63142855U JP S63142855 U JPS63142855 U JP S63142855U JP 1987036375 U JP1987036375 U JP 1987036375U JP 3637587 U JP3637587 U JP 3637587U JP S63142855 U JPS63142855 U JP S63142855U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
device chip
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987036375U
Other languages
Japanese (ja)
Other versions
JPH0526760Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987036375U priority Critical patent/JPH0526760Y2/ja
Publication of JPS63142855U publication Critical patent/JPS63142855U/ja
Application granted granted Critical
Publication of JPH0526760Y2 publication Critical patent/JPH0526760Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図はそれぞれ実施例を示す断面
図、第３図は他の実施例のアイランド部分を示す
側面図、第４図は従来の実装体を示す断面図であ
る。 ２……リードフレーム、４……アイランド、６
……ＩＣチツプ、１０……モールド材、１４，１
８……ポリイミドフイルム、１６……シリコン樹
脂。 1 and 2 are sectional views showing an embodiment, FIG. 3 is a side view showing an island portion of another embodiment, and FIG. 4 is a sectional view showing a conventional mounting body. 2...Lead frame, 4...Island, 6
...IC chip, 10...Mold material, 14,1
8...Polyimide film, 16...Silicone resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードフレームに半導体集積回路装置チツプ等
がワイヤボンデイング法により組み込まれ、その
半導体集積回路装置チツプ等の周囲が樹脂で封止
されている実装体において、前記半導体集積回路
装置チツプ等が固定されているリードフレーム・
アイランドの少なくとも裏面には軟性樹脂層が設
けられていることを特徴とする実装体。 A semiconductor integrated circuit device chip, etc. is fixed in a mounting body in which a semiconductor integrated circuit device chip, etc. is assembled into a lead frame by a wire bonding method, and the periphery of the semiconductor integrated circuit device chip, etc. is sealed with resin. Lead frame·
A mounting body characterized in that a soft resin layer is provided on at least the back surface of the island.
JP1987036375U 1987-03-11 1987-03-11 Expired - Lifetime JPH0526760Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987036375U JPH0526760Y2 (en) 1987-03-11 1987-03-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987036375U JPH0526760Y2 (en) 1987-03-11 1987-03-11

Publications (2)

Publication Number Publication Date
JPS63142855U true JPS63142855U (en) 1988-09-20
JPH0526760Y2 JPH0526760Y2 (en) 1993-07-07

Family

ID=30846719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987036375U Expired - Lifetime JPH0526760Y2 (en) 1987-03-11 1987-03-11

Country Status (1)

Country Link
JP (1) JPH0526760Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260567A (en) * 1996-03-19 1997-10-03 Nec Corp Resin sealed semiconductor device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525584U (en) * 1975-06-27 1977-01-14
JPS533011U (en) * 1976-06-25 1978-01-12
JPS58440U (en) * 1981-06-25 1983-01-05 富士通株式会社 plastic packaging
JPS5988854A (en) * 1982-11-12 1984-05-22 Toshiba Corp Semiconductor device
JPS59116122A (en) * 1982-12-01 1984-07-04 ユニ−・ヴアン・クンストメストフアブリ−ケン・ベスロ−テム・ベンノツトシヤツプ Manufacture of boric acid
JPS59134857A (en) * 1983-01-21 1984-08-02 Toshiba Corp Semiconductor device
JPS60195955A (en) * 1984-03-19 1985-10-04 Hitachi Ltd semiconductor equipment
JPS6123348A (en) * 1984-07-12 1986-01-31 Nec Corp Resin sealing type semiconductor device
JPS61185955A (en) * 1985-02-13 1986-08-19 Toshiba Corp Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439370B2 (en) * 1971-11-20 1979-11-27

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525584U (en) * 1975-06-27 1977-01-14
JPS533011U (en) * 1976-06-25 1978-01-12
JPS58440U (en) * 1981-06-25 1983-01-05 富士通株式会社 plastic packaging
JPS5988854A (en) * 1982-11-12 1984-05-22 Toshiba Corp Semiconductor device
JPS59116122A (en) * 1982-12-01 1984-07-04 ユニ−・ヴアン・クンストメストフアブリ−ケン・ベスロ−テム・ベンノツトシヤツプ Manufacture of boric acid
JPS59134857A (en) * 1983-01-21 1984-08-02 Toshiba Corp Semiconductor device
JPS60195955A (en) * 1984-03-19 1985-10-04 Hitachi Ltd semiconductor equipment
JPS6123348A (en) * 1984-07-12 1986-01-31 Nec Corp Resin sealing type semiconductor device
JPS61185955A (en) * 1985-02-13 1986-08-19 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260567A (en) * 1996-03-19 1997-10-03 Nec Corp Resin sealed semiconductor device

Also Published As

Publication number Publication date
JPH0526760Y2 (en) 1993-07-07

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