JPH02198160A - Resin-encapsulated semiconductor device - Google Patents
Resin-encapsulated semiconductor deviceInfo
- Publication number
- JPH02198160A JPH02198160A JP1016151A JP1615189A JPH02198160A JP H02198160 A JPH02198160 A JP H02198160A JP 1016151 A JP1016151 A JP 1016151A JP 1615189 A JP1615189 A JP 1615189A JP H02198160 A JPH02198160 A JP H02198160A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- header
- header part
- semiconductor device
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 230000001070 adhesive effect Effects 0.000 claims abstract description 9
- 239000000853 adhesive Substances 0.000 claims abstract description 8
- 229920001721 polyimide Polymers 0.000 claims abstract description 7
- 239000009719 polyimide resin Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 238000000465 moulding Methods 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 2
- 239000004642 Polyimide Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000007921 spray Substances 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止半導体装置に関し、主にフルモールド
パッケージ・パワートランジスタを対象とする。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and is mainly directed to a full mold package power transistor.
フルモールドパッケージ・パワートランジスタについて
は、不出願人により出願された特開昭６２−１９３１５
９の「絶縁型半導体装置およびそのモールド型」に記数
されている。Regarding full-molded package power transistors, Japanese Patent Application Laid-Open No. 1983-19315 filed by the non-applicant
9, "Insulated semiconductor device and its mold type".
この絶縁型半導体装置はその製造過程でモールド金型内
にヘッダを浮かせた状聾に保持してレジン（樹脂）を注
入し、チップ及びヘッダの全面をレジンで完全に覆った
形のもので、これにより絶縁板を介することなく配線基
板に実装することができ信頼性を向上するものである。During the manufacturing process of this insulated semiconductor device, the header is held floating in a mold and resin is injected, so that the entire surface of the chip and header is completely covered with resin. This allows mounting on the wiring board without using an insulating plate, thereby improving reliability.
〔発明が解決しよ５とする課題〕
前記フルモールド、トランジスタにおいて、第４図に示
すようにヘッダ２の裏面側ではモールド・レジンが薄く
、ヘッダ２の裏面より一部剥離（９）シてレジンに「裏
面ふくれＪ Ｑｔｌ現象を発生させることがあった。裏
面ふくれ（ｌαが発生した場合、トランジスタ３のθｊ
−ｃ （熱抵抗）がいちじるしく低下し、実装時の熱
破壊の原因となる等の問題が多い。また、ｌ！に面ふく
れを生じた半導体製品は肉眼での外観検査による発見が
難しく、欠陥品を取り除（ことは困難である。このため
、根本的にふくれ発生への対策を講する必要があった。[Problem to be solved by the invention 5] In the full-molded transistor, the mold resin is thin on the back side of the header 2, as shown in FIG. In some cases, the backside bulge JQtl phenomenon occurred in the resin.When the backside bulge (lα) occurred, the θj
-c (thermal resistance) decreases significantly, causing many problems such as causing thermal damage during mounting. Also, l! Semiconductor products with surface blisters are difficult to detect by visual inspection with the naked eye, and it is difficult to remove defective products.Therefore, it was necessary to take fundamental measures to prevent blisters.
本発明の目的は、フルモールド牛導体装置にお〜・て、
ヘッダ長面とモールドレジンの剥離を防止し裏面剥離の
ない牛導体装ｆ１ｔを提供すること忙ある。The object of the present invention is to provide a fully molded conductor device,
It is an object of the present invention to provide a conductor assembly f1t that prevents peeling of the mold resin from the long side of the header and does not cause peeling of the back side.
上記目的は達成するために不発明のレジンモールド牛導
体Ｉ装置は、リードフレームのヘッダ部裏面にモールド
レジンと接着性の良い、丁ｔわち「食い付きの良い」樹
脂もしくは接着剤を塗布した構造とするものである。In order to achieve the above object, the uninvented resin mold conductor I device coats the back side of the header part of the lead frame with a resin or adhesive that has good adhesion to the mold resin, that is, has a "good bite". It is a structure.
上記接着性の良い樹脂乃至接着剤はポリイミド系樹脂乃
至接着剤を使用する。As the resin or adhesive having good adhesive properties, a polyimide resin or adhesive is used.
上記した構成において、制脂はレジン（エポキシｍ脂）
と金属（Ｃｕ ）フレームσ）界面で熱ストレス等に対
して緩衝材の役目を果たすことにより、特にふくれが顕
著に表われ易（・熱ストレスが加わりた場合もヘッダ裏
面とレジンの剥離を防止する。In the above configuration, the anti-grease is resin (epoxy resin)
By acting as a buffer material against thermal stress, etc. at the interface between do.
以下、三端子レギユレータとして使用するトランジスタ
のフルモールドパッケージの実施例について図面Ｖ参照
し説明する。Hereinafter, an embodiment of a full mold package of a transistor used as a three-terminal regulator will be described with reference to Drawing V.
第１図はレジンモールド前のトランジスタの平面図であ
る。FIG. 1 is a plan view of the transistor before resin molding.
第２図にモールド後の正面断面図である。FIG. 2 is a front sectional view after molding.
１はＣｕを′材料とするリードフレームのパターンの一
部であるリード部分である。この中、中央のリードはヘ
ッダ部２と一体に形成されている。Reference numeral 1 denotes a lead portion which is a part of a pattern of a lead frame made of Cu. Among these, the center lead is formed integrally with the header portion 2.
ヘッダ部２はＣｕ版の厚手の部分？有し、その表側には
人ｇめっきが施され、この上九半導体素子（チップ）３
がＡｇペーストにより接続される。Is header part 2 a thick part of the Cu version? The top surface of the semiconductor element (chip) 3 is coated with aluminum plating.
are connected by Ag paste.
ヘッダ部の裏面には、モールド樹脂との食いつきの良い
樹脂、たとえばポリイミド系樹脂４がコーティングされ
ている。The back surface of the header portion is coated with a resin that has good adhesion to the mold resin, such as polyimide resin 4.
上記樹脂４はリードフレームの段階でボンディング部分
をマスクで覆い、スプレィ等によりヘッダ２裏面に塗布
される。The resin 4 is applied to the back surface of the header 2 by spraying or the like, covering the bonding portion with a mask at the lead frame stage.
半導体素子３上のＡ２電極とり−ド１との間はＡ ｕ
線５ Ｋよりて接続（熱圧着ボンディング）される。A u between the A2 electrode on the semiconductor element 3 and the node 1
Connected using wire 5K (thermocompression bonding).
上記ヘッダ２及び素子３の全てを覆ってモールドレジン
（エポキシ樹脂）６により封止されている。The header 2 and the element 3 are all covered and sealed with a mold resin (epoxy resin) 6.
７は貫通孔でネジ等により半導体装置を放熱板に止めて
実装する。Reference numeral 7 denotes a through hole in which the semiconductor device is fixed to the heat sink and mounted using screws or the like.
ヘッダ裏面にはポリイミド系樹脂以外に他の熱硬化性位
（脂接着剤（たとえばシリコーン系樹脂）をコーティン
グしてもよい。これらのコーテイング材は金属ヘッダに
対して強い接着性を有すると轡１時に、モールドレジン
（エポキシ樹脂）に対しても接合性のよい有機樹脂であ
ｎば良く、さらにはその膨張率が金属とモールドレジン
のそれの中間にあることが望ましい。In addition to polyimide resin, the back surface of the header may be coated with another thermosetting adhesive (e.g. silicone resin).These coating materials have strong adhesion to the metal header. In some cases, it is sufficient to use an organic resin that has good bondability to mold resin (epoxy resin), and furthermore, it is desirable that its expansion coefficient be between that of metal and mold resin.
第３図は本発明の他の一実施例を示し、ヘッダ２の裏面
に粗面８を形成しておき、この上にポリイミド系樹脂４
をコーティングすることにより、金属への食い付きを一
層良くすることができる。FIG. 3 shows another embodiment of the present invention, in which a rough surface 8 is formed on the back surface of the header 2, and a polyimide resin 4 is formed on the rough surface 8.
By coating it with , it is possible to make it stick better to metal.
このように、ヘッダ裏面にポリイミド系樹脂等をコーテ
ィングすることで、モールド後にレジンとの剥離を防止
することができ、これにより、締付は実装時の熱抵抗の
バラツキを減少させることができる。In this way, by coating the back surface of the header with a polyimide resin or the like, it is possible to prevent separation from the resin after molding, and thereby the variation in thermal resistance during tightening can be reduced.
不発明によれば前記した構成を有することＫより、以下
の効果を奏する。According to the invention, by having the above-mentioned configuration, the following effects are achieved.
ヘッダ裏面とモールドレジンの剥離がな（なり、ｒａｒ
Ｍフクレ」の発生を防止できる。There is no peeling between the back side of the header and the mold resin.
It is possible to prevent the occurrence of "M blisters".
このことにより、装置の組立の歩留を向上することかで
き、完成品の実装時の熱抵抗のばらつきを減少し、長時
間安定動作する信頼性の大なる牛導体装置Ｖ提供できる
。This makes it possible to improve the assembly yield of the device, reduce variations in thermal resistance during mounting of finished products, and provide a highly reliable conductor device V that operates stably for a long time.
本発明はパワー系フルモールドパッケージング品、パワ
ー系単体素子、ＩＣ全般に利用することができる。The present invention can be used for power system full mold packaging products, power system single elements, and ICs in general.
第１図は不発明の一実施例を示し、７′μモールドトラ
ンジスタのモールド前の平面図である。
第２図は第１図に対応するトランジスタのモールド後の
正面断面図である。
第３図は本発明の他の一実施例を示すトランジスタの一
部拡大断面図である。
第４図は従来例を示し、フルモールドトランジスタの一
部拡大断面図である。
１・・・リード、２・・・ヘッダ、３・・・牛導体チッ
プ、４・・・樹脂コーティング、５・・・Ａｕ線、６・
・・モールドレジン。
第
図
第
図
／−リート・。
Ｚ−ヘーンク・
、ｆ−Ａに悟く
Ｃ−モ−ルドレジン
７一嘘札FIG. 1 shows an embodiment of the invention, and is a plan view of a 7'μ molded transistor before molding. FIG. 2 is a front sectional view of the transistor after molding corresponding to FIG. 1. FIG. 3 is a partially enlarged sectional view of a transistor showing another embodiment of the present invention. FIG. 4 shows a conventional example, and is a partially enlarged sectional view of a full-molded transistor. 1... Lead, 2... Header, 3... Cattle conductor chip, 4... Resin coating, 5... Au wire, 6...
・Mold resin. Figure Figure Figure/-Leet. Z-Henk・, C-Mold Resin 71 Lie bill that realizes f-A
Claims (1)
半導体チップ、半導体チップに接続された複数のリード
及びこれらを包囲する樹脂成形体からなり、上記ヘッダ
の裏面に上記樹脂成形体との接着性の良い樹脂乃至接着
剤がコーティングされていることを特徴とする樹脂封止
半導体装置。 ２、上記樹脂成形体はエポキシ系樹脂であり、コーティ
ングする樹脂乃至接着剤はポリイミド系の樹脂乃至接着
剤である請求項１に記載の樹脂封止半導体装置。[Scope of Claims] 1. A header made of metal, a semiconductor chip attached to the surface of the header, a plurality of leads connected to the semiconductor chip, and a resin molded body surrounding these, the resin molded body being attached to the back surface of the header. A resin-sealed semiconductor device characterized by being coated with a resin or adhesive that has good adhesion to a molded body. 2. The resin-sealed semiconductor device according to claim 1, wherein the resin molded body is an epoxy resin, and the coating resin or adhesive is a polyimide resin or adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1016151A JPH02198160A (en) | 1989-01-27 | 1989-01-27 | Resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1016151A JPH02198160A (en) | 1989-01-27 | 1989-01-27 | Resin-encapsulated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02198160A true JPH02198160A (en) | 1990-08-06 |
Family
ID=11908505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1016151A Pending JPH02198160A (en) | 1989-01-27 | 1989-01-27 | Resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02198160A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002329828A (en) * | 2001-04-27 | 2002-11-15 | Denso Corp | Semiconductor device |
| EP2070113A2 (en) * | 2006-08-11 | 2009-06-17 | Vishay General Semiconductor LLC | Semiconductor device and method for manufacturing a semiconductor device |
-
1989
- 1989-01-27 JP JP1016151A patent/JPH02198160A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002329828A (en) * | 2001-04-27 | 2002-11-15 | Denso Corp | Semiconductor device |
| JP4631205B2 (en) * | 2001-04-27 | 2011-02-16 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| EP2070113A2 (en) * | 2006-08-11 | 2009-06-17 | Vishay General Semiconductor LLC | Semiconductor device and method for manufacturing a semiconductor device |
| EP2070113A4 (en) * | 2006-08-11 | 2011-05-04 | Vishay Gen Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device |
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