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JPS6365655A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS6365655A
JPS6365655A JP61210167A JP21016786A JPS6365655A JP S6365655 A JPS6365655 A JP S6365655A JP 61210167 A JP61210167 A JP 61210167A JP 21016786 A JP21016786 A JP 21016786A JP S6365655 A JPS6365655 A JP S6365655A
Authority
JP
Japan
Prior art keywords
resin
lead frame
semiconductor device
semiconductor element
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61210167A
Other languages
Japanese (ja)
Inventor
Seiichi Nishino
西野 誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61210167A priority Critical patent/JPS6365655A/en
Publication of JPS6365655A publication Critical patent/JPS6365655A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve a device in reliability by a method wherein soldering caused thermal impact that a semiconductor device may experience when it is installed on a printed board is weakened by a coating of a low-stress resin applied to the element installation section of a lead frame. CONSTITUTION:A lead frame element installation section 6 is mounted with a semiconductor element 1 and the semiconductor element 1 is connected by a metal fine wire 2 to an external lead 3. A soft, low-stress silicone resin 5 is applied to the rear surface of the lead frame element installation section 6 and, further, the entirety including the semiconductor element 1 is sealed in an sealing resin 4 that is an epoxy resin or the like. In a device constructed as such, the silicone resin 5 alleviates the thermal impact the device is exposed to when it is installed on a printed board by soldering.

Description

【発明の詳細な説明】 し産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] Industrial application field] The present invention relates to a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の樹脂封止型半導体装置は、リードフレー
ムの素子搭載部に半導体素子を搭載し、金属細線により
半導体素子をリードに接続した後樹脂封止を行なうもの
であり、リードフレームの材質は、一般にFe−Ni合
金又はCu合金から作られ、封止樹脂はエポキシ樹脂が
使用されている。
Conventionally, in this type of resin-sealed semiconductor device, a semiconductor element is mounted on the element mounting part of a lead frame, and the semiconductor element is connected to the leads using thin metal wires and then resin-encapsulated. is generally made from Fe-Ni alloy or Cu alloy, and epoxy resin is used as the sealing resin.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の樹脂封止型半導体装置においては、リー
ドフレームの素子搭載部の裏面は平坦であり、また近年
半導体素子の大型化に伴ない素子搭載部面積も大型化し
ている為に、半導体装置をプリント基板などへ実装する
際のはんだ付は温度で、リードフレームと封止樹脂の膨
張差によって、リードフレームと封止樹脂との界面で剥
れが生じたり、素子搭載部裏面の端部から封止樹脂にク
ラックが入り、半導体装置の信頼性を低下させるという
問題点がある。
In the conventional resin-sealed semiconductor device described above, the back surface of the element mounting portion of the lead frame is flat, and as the size of semiconductor elements has increased in recent years, the area of the element mounting portion has also increased. Soldering when mounting on a printed circuit board, etc. is temperature sensitive, and due to the difference in expansion between the lead frame and the encapsulating resin, peeling may occur at the interface between the lead frame and the encapsulating resin, or peeling may occur from the edge of the back side of the element mounting area. There is a problem in that the sealing resin cracks, reducing the reliability of the semiconductor device.

本発明の目的は、はんだ付は工程において、封止樹脂の
剥れやクラックの発生のない信頼性の向上した樹脂封止
型半導体装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-sealed semiconductor device with improved reliability in which the sealing resin does not peel off or cracks occur during the soldering process.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の樹脂封止型半導体装置は、リードフレ−ムの素
子搭載部に半導体素子を搭載し樹脂封止してなる樹脂封
止型半導体装置であって、前記リードフレームの素子搭
載部の裏面に低応力樹脂を塗布したものである。
The resin-sealed semiconductor device of the present invention is a resin-sealed semiconductor device in which a semiconductor element is mounted on an element mounting portion of a lead frame and sealed with resin, and the back side of the element mounting portion of the lead frame is It is coated with low stress resin.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

第1図において、リードフレームの素子搭載部6には半
導体素子1が搭載されており、この半導体素子1は金属
細線2により外部リード3に接続されている。そして特
に、このリードフレームの素子搭載部6の裏面には軟質
で低応力のシリコーン樹脂5が塗布されており、更に半
導体素子1を含む全体がエポキシ等の封止樹脂4により
封止されている。
In FIG. 1, a semiconductor element 1 is mounted on an element mounting portion 6 of a lead frame, and this semiconductor element 1 is connected to an external lead 3 by a thin metal wire 2. In particular, a soft, low-stress silicone resin 5 is applied to the back surface of the element mounting portion 6 of this lead frame, and the entire body including the semiconductor element 1 is further sealed with a sealing resin 4 such as epoxy. .

このように構成されては本実施例においては、プリント
基板への実装時における、はんだ付けによる熱衝撃をシ
リコーン樹脂5により緩和することができる。
With this structure, in this embodiment, thermal shock caused by soldering during mounting on a printed circuit board can be alleviated by the silicone resin 5.

尚、低応力樹脂としてはシリコーン樹脂の外、ポリイミ
ド樹脂等を用いることができる。
In addition to silicone resin, polyimide resin or the like can be used as the low stress resin.

〔発明の効果〕 以上説明した様に本発明は、リードフレームの素子搭載
部の裏面に低応力樹脂を塗布することにより、半導体装
置がプリント基板へ実装される際のはんだ接続の為の熱
衝撃を緩和出来る効果がある。
[Effects of the Invention] As explained above, the present invention applies a low-stress resin to the back surface of the element mounting portion of the lead frame, thereby reducing thermal shock caused by solder connection when a semiconductor device is mounted on a printed circuit board. It has the effect of alleviating the

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図である。 1・・・半導体素子、2・・・金属細線、3・・・外部
リード、4・・・封止樹脂、5・・・シリコーン樹脂、
6・・・素子搭載部。
FIG. 1 is a sectional view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Metal thin wire, 3... External lead, 4... Sealing resin, 5... Silicone resin,
6...Element mounting section.

Claims (1)

【特許請求の範囲】[Claims] リードフレームの素子搭載部に半導体素子を搭載し樹脂
封止してなる樹脂封止型半導体装置において、前記リー
ドフレームの素子搭載部の裏面に低応力樹脂を塗布した
ことを特徴とする樹脂封止型半導体装置。
A resin-sealed semiconductor device in which a semiconductor element is mounted on an element-mounting part of a lead frame and sealed with resin, characterized in that a low-stress resin is applied to the back side of the element-mounting part of the lead frame. type semiconductor device.
JP61210167A 1986-09-05 1986-09-05 Resin-sealed semiconductor device Pending JPS6365655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61210167A JPS6365655A (en) 1986-09-05 1986-09-05 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61210167A JPS6365655A (en) 1986-09-05 1986-09-05 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6365655A true JPS6365655A (en) 1988-03-24

Family

ID=16584878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61210167A Pending JPS6365655A (en) 1986-09-05 1986-09-05 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6365655A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536970A (en) * 1992-09-29 1996-07-16 Kabushiki Kaisha Toshiba Resin-encapsulated semiconductor device
US5864174A (en) * 1995-10-24 1999-01-26 Oki Electric Industry Co., Ltd. Semiconductor device having a die pad structure for preventing cracks in a molding resin
JP2008239285A (en) * 2007-03-27 2008-10-09 Fujikura Ltd Roll material winding device
EP2070113A2 (en) * 2006-08-11 2009-06-17 Vishay General Semiconductor LLC Semiconductor device and method for manufacturing a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58440B2 (en) * 1971-11-20 1983-01-06 フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ Method for producing 17,21-dihydroxy-20-ketopregnans

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58440B2 (en) * 1971-11-20 1983-01-06 フエルナオ・アウグスト・デ・アラウ−ホ・ヴイセンテ Method for producing 17,21-dihydroxy-20-ketopregnans

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536970A (en) * 1992-09-29 1996-07-16 Kabushiki Kaisha Toshiba Resin-encapsulated semiconductor device
US5864174A (en) * 1995-10-24 1999-01-26 Oki Electric Industry Co., Ltd. Semiconductor device having a die pad structure for preventing cracks in a molding resin
US6177725B1 (en) 1995-10-24 2001-01-23 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US6459145B1 (en) 1995-10-24 2002-10-01 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor
US6569755B2 (en) 1995-10-24 2003-05-27 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
EP2070113A2 (en) * 2006-08-11 2009-06-17 Vishay General Semiconductor LLC Semiconductor device and method for manufacturing a semiconductor device
JP2010500757A (en) * 2006-08-11 2010-01-07 ヴィシャイ ジェネラル セミコンダクター エルエルシー Semiconductor device and manufacturing method of semiconductor device
EP2070113B1 (en) * 2006-08-11 2016-10-05 Vishay General Semiconductor LLC Semiconductor device and method for manufacturing a semiconductor device
JP2008239285A (en) * 2007-03-27 2008-10-09 Fujikura Ltd Roll material winding device

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