JPS60178636A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60178636A JPS60178636A JP59033463A JP3346384A JPS60178636A JP S60178636 A JPS60178636 A JP S60178636A JP 59033463 A JP59033463 A JP 59033463A JP 3346384 A JP3346384 A JP 3346384A JP S60178636 A JPS60178636 A JP S60178636A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- groove
- semiconductor chip
- semiconductor
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract 2
- 238000005219 brazing Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 8
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000002023 wood Substances 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、メサ型素子を用いた半導体装置の構造に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to the structure of a semiconductor device using a mesa type element.
（従来技術）
従来、樹脂封止型半導体装置は、一般に次のように製造
されて込た。即ち、先ず第１図ＩＡ）、１搏。(Prior Art) Conventionally, resin-sealed semiconductor devices have generally been manufactured as follows. That is, first, Figure 1 IA), 1 beat.
ＩＱＫ示す如（、金楓板を所定の形状に力１１工したリ
ードフレーム１のアイランド部１′に半田３を載せ、そ
の上方から半導体チップ２をあて、半導体チップ２に適
尚な荷重を与えることによって半導体チップ２′ｔ−半
田３にてアイランド部１′に固足させ、半導体チップ２
上の電極とリードフレームｌのリードとの間に会則１Ｉ
ａ４等により必要な電気接続を行う、しかる後に第３図
に示す如く樹脂８で半導体チップ２および金ｍ腺４等を
封止し、リードフレーム固足板９を所定位置で切断し、
第４図に示す如き独立した製品の樹脂封止型半導体装置
に分離する。As shown in IQK, solder 3 is placed on the island portion 1' of the lead frame 1, which is made by shaping a gold maple plate into a predetermined shape, and the semiconductor chip 2 is applied from above to apply an appropriate load to the semiconductor chip 2. By this, the semiconductor chip 2' is fixed to the island part 1' with solder 3, and the semiconductor chip 2'
Rule 1I between the upper electrode and the lead of the lead frame l.
After that, as shown in FIG. 3, the semiconductor chip 2 and the gold gland 4 are sealed with resin 8, and the lead frame fixing plate 9 is cut at a predetermined position.
Separate into resin-sealed semiconductor devices as independent products as shown in FIG.
しかしながら、このような従来の半導体装置では、半導
体チップ２を、リードフレームｌｖｃ牛田３を用い固足
させる際、第１図（８，（Ｑに示すようにある程度の荷
重と温度を半導体チップ２とリードフレーム１に加える
為、半田３は半導体チップ２の外側へと流れ出し、マウ
ント強度を低下させると共に樹脂封止の際、シリコン断
面５と半田３のすきまよシ、樹脂８がはいり込み、樹脂
とシリコン基板の熱膨張係数の差によル、半導体基板へ
ストレスを加わえ、特性を劣化させたシ、はなはだしい
場合には半導体チップ２がアイランド部１′から剥離す
る等信頼性に大きな態形」を与えていたｅ
（発明の目的）
不発明の目的は、半導体チップのマウント、固定強度を
同上させると共に樹脂の熱膨張係数による半畳体チップ
への悪影響全防止させ、特性歩留及び旧頓性を大幅に同
上した半導体装置を提供することにある。However, in such a conventional semiconductor device, when the semiconductor chip 2 is fixed using the lead frame lvc Ushida 3, a certain amount of load and temperature are applied to the semiconductor chip 2 as shown in FIG. Since the solder 3 is added to the lead frame 1, it flows out to the outside of the semiconductor chip 2, reducing the mounting strength, and during resin sealing, the resin 8 gets into the gap between the silicon cross section 5 and the solder 3, and the resin and Due to the difference in the coefficient of thermal expansion of the silicon substrate, stress is applied to the semiconductor substrate, resulting in deterioration of its characteristics.In severe cases, the semiconductor chip 2 may peel off from the island portion 1', which may seriously affect reliability. (Objective of the Invention) The object of the invention is to improve the mounting and fixing strength of the semiconductor chip, to completely prevent the adverse effect on the semiconducting chip due to the coefficient of thermal expansion of the resin, and to improve the characteristic yield and obsolescence. An object of the present invention is to provide a semiconductor device which has substantially the same characteristics as those described above.
（発明の構成）
本発明ｅ（よれば、リードフレームの半導体素子載置部
には、半導体素子の接触する部分に溝を有し、この溝内
のはは全体に半導体素子を半田もしくは、ロー桐で取シ
付けた半導体装置を得る。(Structure of the Invention) According to the present invention (e), the semiconductor element mounting portion of the lead frame has a groove in the part where the semiconductor element contacts, and the semiconductor element is soldered or soldered to the entire surface of the groove. Obtain a semiconductor device mounted with paulownia wood.
（発明の実施例）
以下、本発明の一実施例について図面を参照して説明す
る。(Embodiment of the Invention) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第２図（Ａｔ、 ｆ）３）、 ｆ（、’ｌおよび第３図
、第４図は本発明の一実施例の製造工程を示したもので
、まず、リードクレーム１１が作られる。リードフレー
ム１１は金樵板を打ち抜いて外部へ電極を導出するリー
ドと半纏体チップ１２を取シ付けるアイランド１１′
との組を複数組固定板１９で一体化するように形成され
る。アイランド１１′では半導体チップ１２が接触する
而に溝１７が形成されているのそして、第２図（Ｂ）に
示すように半田１３を溝エフの中央部に載せその上に表
裏両面がメサカットされた半導体チップ１２を載せる。Figures 2 (At, f) 3), f(, 'l, Figures 3 and 4 show the manufacturing process of an embodiment of the present invention. First, a lead claim 11 is made. The frame 11 is an island 11' that is made by punching out a metal wood board and attaches a lead for leading out an electrode to the outside and a semi-integrated chip 12.
A fixing plate 19 is used to integrate a plurality of sets. In the island 11', a groove 17 is formed where the semiconductor chip 12 contacts, and as shown in FIG. Then, the semiconductor chip 12 is placed thereon.
次に、第２図（ｑに示すように、半導体チップ１２の上
方から適当な荷重を与えることによって、半導体チップ
１２を溝１７に取り付ける。この時、半田１３は、半導
体チップ１２の下から外側に逃げ、溝１７内に留る。こ
のため、半田１７が半導体チップの外側に流れ出すこと
はなくなり、したがって半導体基板］５と半田】３のす
きまは無くなる。Next, as shown in FIG. 2 (q), the semiconductor chip 12 is attached to the groove 17 by applying an appropriate load from above the semiconductor chip 12. At this time, the solder 13 is applied from the bottom of the semiconductor chip 12 to the outside. The solder 17 escapes and remains in the groove 17. Therefore, the solder 17 does not flow out to the outside of the semiconductor chip, and therefore the gap between the semiconductor substrate [5] and the solder [3] disappears.
その後、第２図（ＡＪに示すように、半導体チップ１２
表面の電極とリード間が全ａ線１４等によって配線がな
される。更に＆第３図に示すように、半導体チップ１２
と全細線１４とを少くとも封止するように樹脂８がモー
ルド等で被覆せられ、第４図［７］−：すように、リー
ドフレーム１１の固矩板１９が切断除去されて個々の半
導体装置ｌＯに分離される。After that, as shown in FIG. 2 (AJ), the semiconductor chip 12
Wiring is performed between the electrodes on the surface and the leads using all A-wires 14 or the like. Furthermore, as shown in FIG.
The resin 8 is coated with a mold or the like so as to seal at least all the thin wires 14, and the solid rectangular plate 19 of the lead frame 11 is cut and removed as shown in FIG. It is separated into semiconductor devices IO.
このように、不実施例によれば半纏体チップ１２を取り
イ」りる半田１３はｍ１７内に留まるので、半導体チッ
プ１２の固定強度は強まシ又％刊止樹脂の態形４を受け
ることはなくなるため、素子特性の劣化がなＩｆ頼性の
高い半導体装置を得ることができる。In this way, according to the non-embodiment, the solder 13 that removes the semi-integrated chip 12 remains within the m17, so that the fixing strength of the semiconductor chip 12 is strengthened and the solder 13 receives the form 4 of the sealing resin. Therefore, it is possible to obtain a semiconductor device with high If reliability without deterioration of element characteristics.
第１図（〜は、従来のメサ型半導体装１鐘（の平面図。
同図（ＩＪＩおよび（Ｃ）は半導体チップ金板９イリけ
る工程ｆ、ボす断面図である。第２図（〜は１本発明の
一実施例による半導体装置の平面図、同図（１（）およ
び（Ｑは半導体チップを取りイ；」ける工程を示す断面
図である０着、３図は４＋＞ｊ脂封止工程後を示す平面
図、第４図は固定板切断後を示す平面図である。
１．１１・・・・リードフレーム、１’、１１’ ・・
・・・−７イラン）”、２． ］ ２・・・・・半導体
チップ、３゜１３・・・・・半Ｂ」、４，１４・・・・
・金細線、５．１５・・・・・半導体チップ側面、６．
ｌｂ・・・・・・ガラス保護膜、１７・・・・・・溝、
８・・・・・・（ｍＪ脂、９． １９・・川・７レーム
固ポ板、１０・・・・・半導体装置、FIG. 1 (- is a plan view of a conventional mesa-type semiconductor device 1). FIG. ~1 is a plan view of a semiconductor device according to an embodiment of the present invention, (1() and (Q) are cross-sectional views showing the process of removing a semiconductor chip, and Figure 3 is a 4+>j FIG. 4 is a plan view showing the state after the fat sealing process, and FIG. 4 is a plan view showing the state after cutting the fixing plate. 1.11...Lead frame, 1', 11'...
...-7 Iran)", 2.] 2... Semiconductor chip, 3゜13...Half B", 4,14...
・Gold thin wire, 5.15...Semiconductor chip side, 6.
lb...Glass protective film, 17...Groove,
8... (mJ fat, 9. 19... River 7 ream solid pot board, 10... Semiconductor device,
Claims (1)
を南し、この溝内に裏面がメサ型に形成された半導体素
子を、半田もしくは、ロー材で取り付けたことを特徴と
する半導体装置。A semiconductor device characterized in that the semiconductor device mounting part has a groove extending south in the area where the semiconductor device contacts, and a semiconductor device whose back surface is formed in a mesa shape is attached to the groove with solder or brazing material. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59033463A JPS60178636A (en) | 1984-02-24 | 1984-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59033463A JPS60178636A (en) | 1984-02-24 | 1984-02-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60178636A true JPS60178636A (en) | 1985-09-12 |
Family
ID=12387233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59033463A Pending JPS60178636A (en) | 1984-02-24 | 1984-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60178636A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104294A (en) * | 1992-09-17 | 1994-04-15 | Nec Corp | Lead frame |
| US5844306A (en) * | 1995-09-28 | 1998-12-01 | Mitsubishi Denki Kabushiki Kaisha | Die pad structure for solder bonding |
| JP2012104709A (en) * | 2010-11-11 | 2012-05-31 | Shindengen Electric Mfg Co Ltd | Lead frame and semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4889060U (en) * | 1972-01-28 | 1973-10-26 | ||
| JPS5039254B1 (en) * | 1970-12-22 | 1975-12-16 | ||
| JPH061550Y2 (en) * | 1987-08-07 | 1994-01-12 | 東海ゴム工業株式会社 | Endless elastic belt |
-
1984
- 1984-02-24 JP JP59033463A patent/JPS60178636A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5039254B1 (en) * | 1970-12-22 | 1975-12-16 | ||
| JPS4889060U (en) * | 1972-01-28 | 1973-10-26 | ||
| JPH061550Y2 (en) * | 1987-08-07 | 1994-01-12 | 東海ゴム工業株式会社 | Endless elastic belt |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104294A (en) * | 1992-09-17 | 1994-04-15 | Nec Corp | Lead frame |
| US5844306A (en) * | 1995-09-28 | 1998-12-01 | Mitsubishi Denki Kabushiki Kaisha | Die pad structure for solder bonding |
| JP2012104709A (en) * | 2010-11-11 | 2012-05-31 | Shindengen Electric Mfg Co Ltd | Lead frame and semiconductor device |
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