JPS61204976A - Thin film transistor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To improve withstanding voltage of a gate, by forming source and drain electrodes by multiple layer films comprising a first conducting film and a low resistance thin semiconductor film on a substrate, and providing the contact between a thin semiconductor film and the source and drain electrodes through the low resistance thin semiconductor film, thereby reducing a leaking current in the reverse direction. CONSTITUTION:A TFT comprises a source electrode 2 and a drain electrode 3, i.e., multiple layer films, which are formed by first conducting films 12 and 13 on an insulating substrate 1 and N<+>a-Si films 22 and 23; an insulating film 7, which covers the side end parts of the multiple layer films and the surface of the substrate 1 between the source and drain electrodes 2 and 3; an a-Si film 4, whose both ends are connected to the N<+>a-Si films 22 and 23; a gate insulating film 5 on the a-Si film 4; and a gate electrode 6. The low resistance thin semiconductor film (e.g., N<+>a-Si film) has, e.g., a hole blocking function. Therefore, a leaking current in the reverse direction can be made small. The presence of the insulating film alleviates the stepped part of the multiple layer films, which are the source and drain electrodes. Thus, the step covering property of the films deposited on the surface can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to thin films using semiconductors such as amorphous silicon (A-SI) and polycrystalline silicon (P-SI). In particular, it relates to the structure of the source and drain C poles of TPT) and its manufacturing method.

[Summary of the invention]

A source and drain α pole consisting of a multilayer film of a thin conductor and a low resistance conductor formed on an insulating base and a first conductor formed thereon;
It consists of a semi-25-body film in contact with the semiconductor film, a gate insulating film provided on the semiconductor film, and a gate.
In 'T, we provide a TFT structure in which the same surface is broken with an insulating film and the contact between the source and drain voltages and the semiconductor 4 is made only through the round resistor semiconductor layer, with less friction. As a result, it is possible to obtain a property with less reverse direction IJ current, and the level difference due to the multilayer film is alleviated, so that the gate flltIE is the same as above. In manufacturing, the insulating film is selectively removed in cell 2 alignment using the multilayer film or its steps before etching the entire surface, and the insulating film covers the sides of the multi-layer roof. is left behind.

[Prior Art] TmT is currently being applied to liquid crystal display devices and the like, and its uses are expanding further. TPT using a-si
Mainly speaking, many structures are possible because it has the characteristic of being able to be deposited in a low potency.

FIG. 2 shows examples 1 to f. TF'r is a source/drain 'If:/72,5 on an insulating substrate 1 and a-sl, which is a semiconductor thin film provided thereon: H
It consists of a gate 4, a gate insulating film 5, and a gate m=6.

Source/drain It 2,5 is usually the first commandment i12,
+5 and n”a-01:H[22
, 25, to reduce resistance and simplify the process. When applying TPT to a liquid crystal display device, a transparent material such as ITO is added to the first conductive layer 12゜15.
It is often used.

Or, as shown in Figure 2, source/drain wiring 62°55
n”a-si 11I!22,
25 or directly contact the first conductive hood +2.15. In order to simplify the manufacturing process, the multilayer film consisting of the fourteenth electric film 12°15 and the n"a-Si films 22 and 25 is selectively etched into the same shape, so that a-81[4 is n"a- While contacting the Si pattern 22, 25, the first conductor 114112. Contact with everyone. The latter contact is a cause of an increase in so-called reverse leakage 141 in the current flowing between the source and drain electrodes when the gate gate is connected, and is unfavorable in terms of off-state characteristics. On the other hand, the selective etching of the multilayer film is the etch latter part 14 of n"a-ei rumors 22 and 25.
Since selective etching is performed at the angle of 12° and 15°, the side surfaces of the multilayer film tend to have a straight, sharp, or reversely tapered shape. A-s on the source/drain electrodes 2,5 with such sides
When forming i-sig 4, gate e-edge 1 return 5, and gate kai-poku 6, the level difference in these gates is not sufficiently chronic, resulting in a short circuit between gate Akebono 11 and a-sig 4 at the stepped part, or a breakdown voltage failure. As a result, there was a problem in that the performance of the RD T device was not improved.

[Problems to be Solved by the Invention] The present invention has been made in consideration of the above-mentioned problems, and the first object is to provide a TF''T with less reverse leakage. The second purpose is to improve gate breakdown voltage. The fifth objective is to provide an easy manufacturing method for the above purpose.

[Failure to solve the problem]

The TPT according to the present invention has source/drain electrodes formed of a multilayer film consisting of a first sleep-inducing layer and a low-resistance semiconductor layer provided on an insulating substrate, and a side surface of the multilayer layer and a space between the layers. It has a structure in which the surface of the substrate is covered with an insulating film.

Since a semiconductor thin film, a gate insulating film, and a gate electrode are provided thereon, the semiconductor thin film contacts only the low-resistance semiconductor thin film of the multilayer film.

[Effect]

Due to the above structure, the resistive semiconductor/lφ (e.g. n“a
-siI! Since i) has, for example, a hole blocking function, the reverse leakage current can be reduced. In addition, the presence of the IP3 edge reduces the step difference in the multilayer film that is the source/drain electrode, so that the step coverage of - deposited thereon can be improved.

〔Example〕

(a) Actual Example I TPT cross section (SiN2 diagram) An example of the vfr surface of the TIFT structure according to the present invention is shown in FIG.

TIFT is a first conductive layer 12°15 and n on an insulating substrate 1.
an insulating film 7 that covers the source ta2 and drain electrode 5, which are multilayer films consisting of +a-θ1 electrodes 22 and 25, and the side edges of the multilayer film and the surface of the substrate 10 between the source and drain electrodes 2 and 5; n”a-8 with both ends touching 22゜25
Consists of 1 movie 4, A-81 暎4 on gate, eegs and game) $46. In this example, the source/drain wiring 52.55 provided as necessary is in contact with the first conductive film 12.15 of each electrode 2.3. The insulating substrate 1 is made of an insulating material such as glass, quartz, or ceramics (c81 or metal coated with an absolute IIR* coating).
In addition to metals such as R, W, Mo, and Ti, especially high-melting point metals and their silicides, transparent conductors such as Tonne are also used, and multilayer films of these materials may also be used. ,810
In addition to X, 5iNX%, an organic insulating film such as polyimide may also be used. n”a-si exchange 22°25 and a-sil14
Although a-si:H alloy, a-si:F alloy, etc. are used, p-si and beam annealed 81 thin film are also applicable. n”a-θ1ll122°25 is pea-s
It is also possible to change 11 to i@ for Mg.

The present invention will be further clarified by explaining the manufacturing method when the present invention is applied to a TPT substrate for a liquid crystal display device.

(1)) Example 2 Unit pixel cross section (@Figure 5) No. 5
Figure (a) shows a transparent 1P3Iij made of glass, quartz, etc. and a transparent groove '11111 which is the first conductive layer 12.15 on the substrate i.
1! (For example, To (L1μ) +02.+05 and the impermeable groove '4g (for example, gold M film α+μ) I t2.+ +
5 tvz layer complaints and n”a-si complaints 22, 25 (e.g. 5
After depositing 0()s) and these poly rtl tjl
'(+- This is the 1!!l? plane selectively left in the shape of the source electrode 2 and drain electrode S. Figure S (b) shows the insulation 1
1g! 7 is deposited on the entire surface, a negative resist 8 is coated, exposed to light from the back side, and developed. Insulating film 7 is 5iO
CVD process such as 1k11/%: -511 (1"S, lj"l'1i4se-(1
＞・Toru −f+Ii4〜−・Metal films 112, 11 by light
5 serves as a mask, and the resist 8 can be left in a self-aligned manner. In order to cover the 1m11A side surface of each electrode 2.5 with the insulating film 7 by the amount of light, either make the back side light 4 over or bake it at a degree that the resist 8 is key-shaped! 11”
It is embarrassing to spread the resist 8 to the surfaces of 5L-8111i22 and 25. FIG. 5(c) shows a state in which 11 bullets 7t-selective etching has been performed using the resist 8 as a mask. It is effective to gently etch the end portion 17 of the insulating film 7, and sputtering, ion etching, etc. are effective.

FIG. 5(d) shows a state in which a-sin 4, a gate insulating film 5, and a gate-electrode metal I (for example, l)+6 are deposited in sequence. a-sin (for example, tld'500X) 4, gate insulating film (for example, SiNx α2μ) 5 is plasma
It can be deposited with vb, but n"a- is deposited before a-si film is deposited.
si 1122, 259 side Hl or A? It is desirable to purify m at i%. slA<θ) is the completed TP
As an example of the T structure, after forming the gate formation 6 by selective etching, the gate insulating film 5, a-s, is formed by the next mask process.
In4 is selectively etched, and the exposed n"a-1, trunk 25, and gold layer 115 are removed (7). Through this final step, IToql+, which is a part of the drain electrode 5, is removed.
05 is a transparent pixel. metal t1gl12. IIS is n
Although it is not necessarily necessary if the a-si lines 22 and 25 are sufficiently thick, it is effective in improving the masking effect of the back exposure in FIG. 5(f) and reducing the wiring resistance.;fe) Example 5 Source・Formation of drain electrode (Figure 4) Figure 4 shows another method for forming the source, drain, and in electrodes according to the present invention. Figure 4 (-) shows the insulating substrate l (transparent). (Doesn't have to be) On the 1st lead '1m512.15
This shows the state in which the source/drain electrodes 2.5 are formed of a multiplicity of n"a-aim 22 and 25.
Figure (f) shows a state in which an ink @7 is applied, which allows for thicker deposition on the four parts. In this case, in addition to the above-mentioned Yombu insulation
? An insulating film formed by bias sputtering is also effective. Next, by stopping the etching in the middle of removing the insulating film 11J17 on the entire surface, the insulating film 7 can be left buried between the source and drain electrodes 2.3 as shown in FIG. 4(c). . After this, if a-81 membrane 4 is formed, gate MI3 edge waist 5 is formed, gate '1t, and section 6 is formed, TP is completed.
T is completed.

As an application of this example, it is also possible to further coat a resist or the like in the state shown in FIG. 4(f) to flatten the surface, and then etch the entire surface by dry etching or the like at approximately the same etch rate for the resist and the insulating film 7. I can do it.

(d,) Example 4 Formation of source/drain round objects (
FIG. 5) FIG. 5 shows an example in which a photosensitive insulating film is used as the insulating film 7. In Fig. 5 Ca), ■'rol is placed on the transparent insulating substrate 1.
oz, +05, metal 112. +15, +1”a-s
ifil! After forming source/drain electrodes 2.5 consisting of 22 and 25, the entire surface is coated with a photosensitive insulating film (for example, negative type polyimide resin) 7. In this state, by exposing the substrate to light from the long surface and developing it, an insulating film 7 covering 11 surfaces of the source/drain electrodes 2.5 can be formed as shown in FIG. 5(f). For these 4 events as well, over 4 light is desirable. In addition, the part 17 of the insulation s7
In order to further smoothen the surface area, etching using oxygen plasma, ion etching, sputter etching, etc. are effective.

〔Effect of the invention〕

As described above, the present invention can reduce the reverse IJ-ret flow and increase the gate breakdown voltage by flattening the gate through simple steps. Since the present invention mainly relates to the source/drain electrode structure and its manufacturing method, it is applicable to all TPT structures and manufacturing methods in which A-SI, gate insulating film, and gate wL pole are formed after forming the source/drain electrodes. In the present invention, since the insulating film 7 can be selectively formed in a self-aligned manner, it can be applied to large-area TPT devices, fine TPT devices, etc., and the characteristics and yield can be improved.

We have mainly described examples of using a-si for semiconductor thinning, but
p-81, beam annealed semiconductor tint, and s
It can be applied not only to i but also to other semiconductor thin films.

Furthermore, since the TPT according to the present invention can easily flatten the source/drain' poles, semiconductor thin reflection can be avoided.
Effective when extremely thin as aX, Dingsemi/7-1! -7shi L-north 1/l” point 18mu :e center 1aJ h
<-im 7- r l-a: I can do it.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a TPT according to the present invention, FIG. 2 is a sectional view of a conventional TUFT, and FIG. Forward sectional views, Figs. 4(a)-(c) and Figs. 5(a) and jb
) are cross-sectional views showing the steps of an embodiment of a method for forming a source/drain electrode structure. ...Substrate 2...Source rtB S...Drain electrode 4...A-SI, rumor 5...Gate insulating film 6
...Gaiter pole 7...Insulation m+2. sΔ...1st conductor 22, 25--o"ts-st hood 102
．． +05-1T. 112.115... Metal layer or more Applicant: Seiko Kuko Kogyo Co., Ltd. The present invention ('-TFT Meh Koma diagram ¥y1 diagram Conventional TFTIQMf1 diagram Figure 2

Claims (7)

[Claims] (1) an insulating substrate, a source electrode and a drain electrode formed apart from each other on the substrate, a semiconductor thin film whose ends are in contact with the source and drain electrodes, and a gate insulating film provided on the thin film; In a thin film transistor consisting of at least a gate electrode provided on the insulating film, the source and drain electrodes are a multilayer film consisting of a first conductive film and a low-resistance semiconductor thin film from the substrate side; Insulation is provided to cover at least the same side surface of the substrate surface and the multilayer film that is the source and drain electrodes, and the semiconductor thin film and the source and drain electrodes are contacted through the low resistance semiconductor thin film. thin film transistor device. (2) The thin film transistor device according to claim 1, wherein at least a common portion of the first conductive film is a transparent conductive film. (3) The thin film transistor device according to claim 1 or 2, wherein the insulating film is a coated insulating film, and the step difference in the multilayer film serving as the source and drain electrodes is alleviated. (4) (a) First step of sequentially depositing a first conductive film and a low-resistance semiconductor thin film on an insulating substrate to form a multilayer film (b) Selectively forming the multilayer film in island-like regions in the shape of source and drain electrodes Second step (c) Depositing an insulating film on the entire surface. Third step (d) Using the multilayer film or steps of the multilayer film, remove the insulating film on the multilayer film, and remove the insulating film on the substrate and the multilayer film. A method for manufacturing a thin film transistor device comprising a fourth step (e) in which the insulating film is left so as to cover the side surfaces of the film; and a fifth step (e) in which a semiconductor thin film, a gate insulating film, and a gate electrode are sequentially formed. (5) Manufacturing the thin film transistor device according to claim 4, wherein the substrate is transparent, and the fourth step utilizes light exposure from the back side of the substrate using the multilayer film as a mask. Method. (6) The method for manufacturing a thin film transistor device according to claim 4 or 5, wherein in the third step, the insulating film is deposited by coating. (7) The fourth step is characterized in that the entire surface of the insulating film is etched by utilizing a difference in thickness between the insulating film on the substrate and the multilayer film caused by a step difference in the multilayer film. A method for manufacturing a thin film transistor device according to claim 6.