JPH10173195A - Thin film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a highly reliable normal staggered thin film transistor at a low cost, by patterning an ITO film on an interlayer insulating film to form source and drain electrodes and introducing phosphorus to the surface of the ITO film by the PH3 (phosphine) plasma doping method, for forming an amorphous silicon layer of an active layer on the ITO film to form an ohmic contact on the electrodes. SOLUTION: A thin film transistor is constituted by forming a metallic film pattern 2 on a transparent insulating substrate 1 and entirely covering the pattern 2 with an interlayer insulating film of silicon nitride 3, and then, separately forming source and drain electrodes 4 and 4 composed of transparent conductive films containing phosphorus introduced into their surfaces on the surface of the interlayer insulating film 3 and a semiconductor film 6, a gate insulating film of silicon nitride 7, and a gate electrode 8 on the electrodes 4 and 4. The pattern 2 is also used as a back gate electrode 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display device and the like and a method for manufacturing the same, and more particularly to a forward staggered thin film transistor using a silicon nitride film as a base for source / drain electrodes and a method for manufacturing the same.

[0002]

2. Description of the Prior Art FIGS. 5A to 5C show a conventional process of manufacturing a forward stagger type thin film transistor.

[0005] First, as shown in FIG. 5A, an Indium Ti film serving as a source / drain electrode is formed on a glass substrate 1.
After an n-oxide film (hereinafter, referred to as an ITO film) is formed by a sputtering method, patterning is performed using ordinary photolithography and etching techniques to obtain the source / drain electrodes 4.

Next, in FIG. 5B, phosphine (P) is formed to form an ohmic contact with the semiconductor layer.
H ₃ ) Plasma treatment with phosphorus 5 for source / drain electrodes 4
Adheres to the surface of the ITO film.

Next, in FIG. 5C, an amorphous silicon film 6 and a silicon nitride film 7 serving as a gate insulating film are
-A continuous film is formed by a CVD method, a metal film 8 to be a gate electrode is formed by a sputtering method, and the metal film 8, the silicon nitride film 7, and the amorphous silicon film 6 are formed by using a usual photolithography and etching technique. Once P
By patterning in the R step, a forward staggered thin film transistor as shown in FIG. 5C is completed.

A thin film transistor having this structure is known, for example, from Japanese Patent Publication No. 6-22244, and is disclosed in Japanese Unexamined Patent Publication No. 62-81057.
The structure is the same except that the film is used.

Japanese Patent Application Laid-Open No. Hei 4-233777 is the same as Japanese Patent Publication No. 6-22244 in that phosphorus is plasma-doped on a source / drain electrode formed of an ITO film formed on a glass substrate.

In the structure of these known examples, when actually applied to a color liquid crystal display device, since a thin film transistor is formed directly on a transparent glass substrate, light is applied to the back channel portion of the thin film transistor from the back surface of the substrate, and the transistor is formed. There is a problem that the device does not operate normally due to light sensitivity.

When applied to a color liquid crystal display device, for example, a structure in which a light-shielding film is arranged below a back channel portion as disclosed in Japanese Patent Application Laid-Open No. 7-162007 is suitable.

In Japanese Patent Application Laid-Open No. 7-162007, a metal film pattern serving as a light-shielding film is formed on a transparent glass substrate.
An insulating film is formed, an ITO film pattern serving as a source / drain electrode is formed thereon, phosphorus ions are implanted into the source / drain electrode surface by an ion doping method, and an amorphous silicon film is formed by a plasma CVD method.
In this structure, a molybdenum film is formed as a gate electrode.

[0011]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 7-162.
In the thin film transistor disclosed in Japanese Patent Application Publication No. 007, a light-shielding film is formed on an insulating substrate, an insulating film made of a silicon oxide film is formed to cover the light-shielding film, and a pixel electrode and a source made of a transparent conductive ITO film are formed. An electrode and a drain electrode are formed, an n ⁺ layer is formed on the source electrode and the drain electrode,
In this structure, an amorphous silicon film serving as a channel is formed, and a gate insulating film and a gate electrode are formed over the amorphous silicon film.

As described above, since the insulating film that is the base of the source electrode and the drain electrode and is in contact with the back channel interface of the thin film transistor is a silicon oxide film, the threshold voltage of the transistor fluctuates, and the first problem is that reliability is poor. Having.

The reason is that many mobile ions exist in the silicon oxide film, and the transistor characteristics fluctuate.

The second problem is that, when a contact hole is formed in a base (interlayer) insulating film by a dry etching method to make contact with a back gate electrode, the etching time is long, the throughput is reduced, and the manufacturing cost is increased. It is. .

The reason is that a silicon oxide film formed by a sputtering method has a low etching rate in a dry etching apparatus since a dense film is formed.

A third problem is that when the underlying (interlayer) insulating film is formed of a silicon oxide film, a sputtering apparatus dedicated to this step is required, and the manufacturing cost is increased.

The reason is that in order to obtain highly reliable transistor characteristics in a thin film transistor manufacturing process, a gate insulating film made of a silicon nitride film formed by a plasma CVD device is essential, and two types of film forming devices are required. This is because

Accordingly, it is an object of the present invention to provide a thin film transistor and a method of manufacturing the same that can improve the reliability and reduce the manufacturing cost of a forward staggered thin film transistor array used in a color liquid crystal display device.

[0019]

A feature of the present invention is that a metal film pattern is formed on a transparent insulating substrate, the entire metal film pattern is covered with an interlayer insulating film of silicon nitride, and a phosphorous surface is formed thereon. A source electrode and a drain electrode made of a transparent conductive film into which are introduced are formed separately from each other, and a semiconductor film is formed on at least a part of each of the source electrode and the drain electrode and between the source electrode and the drain electrode. There is a thin film transistor in which a gate insulating film of silicon nitride having the same pattern is formed on the semiconductor film and a gate electrode is formed on the gate insulating film. Here, the metal pattern may be a light shielding film or a back gate electrode also serving as a light shielding film.

Another feature of the present invention is that a first step of forming a metal film pattern on a transparent insulating substrate and a second step of forming an interlayer insulating film made of a silicon nitride film covering the entire metal film pattern. A third step of forming a source electrode and a drain electrode by patterning a transparent conductive film on the interlayer insulating film, and a fourth step of introducing phosphorus as an impurity into the surfaces of the source electrode and the drain electrode. A fifth step of sequentially forming a semiconductor layer serving as an active layer of the thin film transistor, an insulating layer serving as a gate insulating film, and a conductive layer serving as a gate electrode; And a sixth step of patterning so as to cover the source electrode and the drain electrode. Here, the step of forming the interlayer insulating film in the second step and the step of forming the semiconductor layer and the gate insulating film in the fifth step are performed by plasma CVD.
It is preferably formed by a method.

Another feature of the present invention is that a first step of forming a light-shielding film and a metal film pattern serving as a first gate electrode on a transparent insulating substrate and a silicon nitride film covering the entire metal film pattern are provided. Forming a source electrode and a drain electrode by patterning a transparent electrode film on the interlayer insulating film; and forming a source electrode and a drain electrode on the surface of the source electrode and the drain electrode. A fourth step of introducing phosphorus as an impurity, a fifth step of sequentially forming a semiconductor layer serving as an active layer of the thin film transistor and an insulating layer serving as a first gate insulating film, and forming at least the insulating layer and the semiconductor layer. A sixth step of patterning a part so as to cover the source electrode and the drain electrode, and covering the whole of the source electrode, the drain electrode, the semiconductor layer, and the insulating layer pattern A seventh step of forming a second gate insulating film, an eighth step of forming a contact hole in the first gate insulating film and the second gate insulating film, and forming the second gate electrode, A method of manufacturing a dual-gate thin film transistor, comprising: a ninth step of forming a conductive layer that makes contact with the first gate electrode through a contact hole; and a tenth step of patterning the conductive layer. .

According to the present invention, the interlayer insulating film serving as the base of the source / drain electrodes is composed of a silicon nitride film. (1) The silicon nitride film is smaller than the conventional silicon oxide film.
Since the number of movable ions in the film is small, the change in threshold voltage is small, and the reliability of transistor characteristics is further improved.

(2) In the step of forming a contact hole in the interlayer insulating film by dry etching and making contact with the back gate electrode, the silicon nitride film has a faster etching rate than the silicon oxide film, and the processing time is short. Throughput is increased and manufacturing costs are reduced.

(3) Since the interlayer insulating film is formed of the same silicon nitride film as the gate insulating film, a sputtering device for forming a silicon oxide film is not required, and both films can be formed by the same manufacturing apparatus. Therefore, the manufacturing cost is reduced.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a staggered thin film transistor according to a first embodiment of the present invention. As shown in FIG. 1, a conductive metal film 2 made of, for example, Cr serving as a light-shielding film is disposed on a glass substrate 1, and an interlayer insulating film 3 made of a silicon nitride film is covered thereon.

Then, on the interlayer insulating film 3, a source / drain electrode 4 composed of an ITO film 4 having phosphorus introduced into the surface thereof in a phosphine (PH ₃ ) plasma after patterning is arranged. A stacked pattern of an amorphous silicon film 6 serving as an active layer of a thin film transistor, a gate insulating film 7 formed of a silicon nitride film, and a gate electrode 8 formed of a Cr film is arranged.

Here, the amorphous silicon film 6 is ohmically connected to the source / drain electrodes 4 by the ITO film with phosphorus introduced into the surface.

Next, a method of manufacturing a staggered thin film transistor according to the first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2A, a chromium film is formed on the glass substrate 1 to a thickness of about 200 nm by a sputtering method, and is patterned by ordinary photolithography and etching. The light shielding film 2 is formed.

Next, as shown in FIG. 2B, a silicon nitride film is formed from 200 nm to 400 nm by a plasma CVD method.
After forming the interlayer insulating film 3 by forming a film having a thickness of m, an ITO film 4 for forming a pixel electrode, a signal line, and a source / drain electrode is formed.

Next, as shown in FIG. 2C, an ITO film pattern 4 serving as a source / drain electrode is formed by a usual photolithography method and etching method.
TO film 4 and amorphous silicon film 6 laminated thereon
To form an ohmic contact with the pixel electrode,
Plasma CV on the surface of the signal line and source / drain electrode 4
Phosphine (PH ₃ ) plasma treatment with D
Phosphorus 5 is selectively doped on the film surface.

At this time, since the surface of the silicon nitride film 3, which is the base of the pixel electrode, the signal line, and the source / drain electrode, is not doped with phosphorus, the characteristics of the transistor are not affected.

Next, following the phosphine (PH ₃ ) plasma treatment, an amorphous silicon film 6 having a thickness of about 50 nm and a silicon nitride film having a thickness of about 400 nm to be a gate insulating film 7 are formed by P-CVD. Form a continuous film.

Further, in order to form the gate electrode 8, Cr
A film is formed to a thickness of 100 to 200 nm by a sputtering method (FIG. 2D), and a gate electrode 9, a gate insulating film 8, and an amorphous silicon film 7 are formed by a single photomask process by a normal photolithography method. Then, a staggered thin film transistor as shown in FIG. 2E can be obtained.

Next, FIG. 3 shows the amount of change in the threshold voltage with respect to the bias application time when a silicon nitride film is used as a base insulating film and when a silicon oxide film is used.

As can be seen from FIG. 3, the variation of the threshold voltage is smaller when the silicon nitride film is used as the insulating film. This is because there are more mobile ions in the silicon oxide film than in the silicon nitride film.

Therefore, according to the present invention, it is possible to obtain a highly reliable thin film transistor having stable characteristics and a small variation in threshold voltage.

Further, since the interlayer insulating film is the same silicon nitride film as the gate insulating film, a sputtering apparatus which was conventionally required for growing a silicon oxide film having a high withstand voltage as the interlayer insulating film becomes unnecessary. Since the interlayer insulating film can be obtained by the same plasma CVD device as the gate insulating film, the manufacturing cost can be reduced.

Next, a second embodiment of the present invention will be described. 4A to 4E are cross-sectional views illustrating a method of manufacturing a staggered thin film transistor according to a second embodiment of the present invention in the order of steps.

First, as shown in FIG. 4A, a chromium (Cr) film is formed on the glass substrate 1 to a thickness of about 200 nm by a sputtering method, and is patterned by ordinary photolithography and etching. Then, a back gate electrode 2a also serving as a light-shielding film is formed, and a silicon nitride film serving as an interlayer insulating film 3 is formed by a plasma CVD method from 200 to 400.
The film is formed to a thickness of nm.

Next, as shown in FIG. 4B, an ITO film is formed and patterned by a usual photolithography method and an etching method to form an ITO film 4 serving as a pixel electrode, a signal line and a source / drain electrode. Is formed. Thereafter, in order to form an ohmic contact between the ITO film 4 and the amorphous silicon film 6 laminated thereon, phosphine (PH ₃ ) is formed on the surfaces of the pixel electrode, the signal line, and the source / drain electrode 4 by a plasma CVD apparatus.
Plasma treatment is performed to selectively dope phosphorus 5 on the surface of the ITO film. At this time, the surface of the silicon nitride film 3, which is the base of the pixel electrode, the signal line, and the source / drain electrode, is not doped with phosphorus, so that the transistor characteristics are not affected.

Next, as shown in FIG. 4 (C), the film thickness is about 50 nm, following the phosphine (PH ₃ ) plasma treatment.
A silicon nitride film having a thickness of about 400 nm, which becomes the amorphous silicon film 6 and the gate insulating film 7, is continuously formed by a P-CVD method, and is patterned by a usual photolithography method and an etching method.

Next, as shown in FIG. 4D, a silicon nitride film having a thickness of about 200 nm to be the second gate insulating film 7a is formed by the P-CVD method.

Next, as shown in FIG. 4E, the second gate insulating film 7a and the interlayer insulating film 3 are contacted with the back gate electrode 2a also serving as a light shielding film and the wiring.
SF ₆ + He, CF ₄ + O ₂ + with dry etching equipment
A contact hole is opened using a gas system such as He.

Thereafter, a Cr film serving as a gate electrode and a wiring is formed to a thickness of 100 to 200 nm by a sputtering method, and a gate electrode 8 and a wiring are formed by a usual photolithography method and an etching method. A thin film transistor can be obtained. In the step of making a contact hole in the interlayer insulating film by using a gas system such as SF ₆ + He or CF ₄ + O ₂ + He with a dry etching apparatus and making contact with the back gate electrode 2 also serving as a light shielding film, a conventional sputtering method is used. Than the silicon oxide film formed in
Since the silicon nitride film formed by the plasma CVD method has a high etch rate, the etching time is shortened, the throughput is improved, and the manufacturing cost can be reduced. That is, the etching rate of the silicon oxide film formed by the sputtering method is about 10% slower than that of the silicon oxide film obtained by the plasma CVD method.

Further, similarly to the first embodiment of the present invention, it is possible to obtain a highly reliable thin film transistor having a small variation in the threshold voltage and a stable characteristic, similar to the first embodiment. In addition, since the interlayer insulating film is the same silicon nitride film as the gate insulating film, the second gate insulating film and the interlayer insulating film can be obtained with the same plasma CVD device as the gate insulating film, so that the manufacturing cost can be reduced. Can be planned.

In the thin film transistor having the structure of the first embodiment, a light shielding film is formed on the back channel side of the transistor in order to limit the light sensitivity characteristics of the transistor due to light incident from the transparent substrate side. In the thin film transistor having the structure of the second embodiment, the formation of the light-shielding film on the back channel side is the same as that of the thin-film transistor. different.

Therefore, the number of steps for manufacturing the thin film transistor array is the same, and the manufacturing cost is the same.

The dual-gate forward staggered thin film transistor having the structure of the second embodiment has improved transistor characteristics and reliability, such as improved mobility, as compared with the thin film transistor having the structure of the first embodiment. I do.

[0051]

The first effect is that the variation in the threshold voltage of the transistor characteristics is small and the reliability is improved.

The reason is that the silicon nitride film has less mobile ions than the silicon oxide film.

The second effect is that, since the etching time for forming the contact hole is short, the production efficiency is increased, and the production cost is reduced.

The reason for this is that the silicon nitride film formed by the P-CVD method has a higher etching rate in the dry etching process than the formed silicon oxide film formed by the sputtering method.

A third effect is that a sputtering device for forming a silicon oxide film is not required, and the manufacturing cost can be reduced.

The reason is that the interlayer insulating film is the same silicon nitride film as the gate insulating film, and can be formed by the same plasma CVD apparatus.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a forward staggered thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing the thin film transistor shown in FIG.

FIG. 3 is a diagram showing a threshold voltage variation of the forward staggered thin film transistor according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a staggered thin film transistor according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing a method of manufacturing a conventional staggered thin film transistor in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Light shielding film 2a Back gate electrode 3 Interlayer insulating film 4 Source / drain electrode 5 Phosphorus 6 Amorphous silicon film 7 Gate insulating film 7a Second gate insulating film 8 Gate electrode

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 619B

Claims (5)

[Claims] A metal film pattern is formed on a transparent insulating substrate, the entire metal film pattern is covered with an interlayer insulating film of silicon nitride, and a source made of a transparent conductive film having phosphorus introduced on a surface thereof. An electrode and a drain electrode are formed separately from each other, a semiconductor film is formed on at least a part of each of the source electrode and the drain electrode, and between the source electrode and the drain electrode, and on the semiconductor film,
A thin film transistor, wherein a gate insulating film of silicon nitride having the same pattern is formed, and a gate electrode is formed on the gate insulating film. 2. The thin film transistor according to claim 1, wherein the metal pattern is a light shielding film or a back gate electrode also serving as a light shielding film. 3. A first step of forming a metal film pattern on a transparent insulating substrate; a second step of forming an interlayer insulating film made of a silicon nitride film covering the entire metal film pattern; A third step of forming a source electrode and a drain electrode by patterning a transparent conductive film on the film, a fourth step of introducing phosphorus as an impurity to the surfaces of the source electrode and the drain electrode, and an active layer of the thin film transistor. A fifth step of sequentially forming a semiconductor layer to be formed, an insulating layer to be a gate insulating film, and a conductive layer to be a gate electrode; and forming at least a part of the conductive layer, the insulating layer and the semiconductor layer into the source electrode and the drain. And a sixth step of performing patterning so as to cover the electrode. 4. The method according to claim 3, wherein the step of forming the interlayer insulating film in the second step and the step of forming the semiconductor layer and the gate insulating film in the fifth step are performed by a plasma CVD method. Method for manufacturing thin film transistor. 5. A first step of forming a light-shielding film and a metal film pattern serving as a first gate electrode on a transparent insulating substrate, and forming an interlayer insulating film made of a silicon nitride film covering the entire metal film pattern. A second step of forming a transparent electrode film on the interlayer insulating film to form a source electrode and a drain electrode; and introducing phosphorus as an impurity into the surfaces of the source electrode and the drain electrode. A fourth step, a fifth step of sequentially forming a semiconductor layer to be an active layer of the thin film transistor and an insulating layer to be a first gate insulating film, and at least part of the insulating layer and the semiconductor layer being the source electrode. And a sixth step of patterning the drain electrode and the source electrode,
A seventh step of forming a second gate insulating film covering the whole of the drain electrode, the semiconductor layer, and the insulating layer pattern;
An eighth step of forming a contact hole in the gate insulating film and the second gate insulating film, and conducting the second gate electrode and making contact with the first gate electrode through the contact hole. A method for manufacturing a thin film transistor, comprising: a ninth step of forming a layer; and a tenth step of patterning the conductive layer.