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JPS62216372A - A-si thin film transistor - Google Patents

A-si thin film transistor

Info

Publication number
JPS62216372A
JPS62216372A JP61060047A JP6004786A JPS62216372A JP S62216372 A JPS62216372 A JP S62216372A JP 61060047 A JP61060047 A JP 61060047A JP 6004786 A JP6004786 A JP 6004786A JP S62216372 A JPS62216372 A JP S62216372A
Authority
JP
Japan
Prior art keywords
thin film
film transistor
active layer
gate
drain electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61060047A
Other languages
Japanese (ja)
Inventor
Tadahisa Yamaguchi
山口 忠久
Tetsuzo Yoshimura
徹三 吉村
Koichi Hiranaka
弘一 平中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61060047A priority Critical patent/JPS62216372A/en
Publication of JPS62216372A publication Critical patent/JPS62216372A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]

Landscapes

  • Thin Film Transistor (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概要〕 トップ・ゲート・スタガ型のa−3i薄膜トランジスタ
において、ソース電極とドレイン電極との間の凹部を無
機薄膜で埋めて、ソース電極およびドレイン電極と基板
との間の段差をなくし、その上に形成されるa−Si活
性層をプレーナ化することににより、a−3i活性層の
断膜を防止する。
[Detailed Description of the Invention] [Summary] In a top-gate staggered a-3i thin film transistor, the concave portion between the source electrode and the drain electrode is filled with an inorganic thin film, and the gap between the source electrode and the drain electrode and the substrate is By eliminating the step difference and planarizing the a-Si active layer formed thereon, breakage of the a-3i active layer is prevented.

〔産業上の利用分野〕[Industrial application field]

a−Si (アモルファスシリコン)活性層を利用する
電界効果トランジスタには、絶縁基板側にソース電極と
ドレイン電極を有するトップ・ゲート・スタガ型と、逆
に絶縁基板側にデーl−電極を有し、最上部にソース電
極とドレイン電極を有する逆スタガード型がある。本発
明は、前者のトップ・ゲート・スタガ型のa−3il膜
トランジスタに関する。
Field-effect transistors using an a-Si (amorphous silicon) active layer include a top-gate staggered type that has a source electrode and a drain electrode on the insulating substrate side, and a top-gate staggered type that has a data electrode on the insulating substrate side. , there is an inverted staggered type that has a source electrode and a drain electrode at the top. The present invention relates to the former top gate staggered A-3IL film transistor.

〔従来の技術〕[Conventional technology]

第3図は従来のトップ・ゲート・スタガ型のa−Si薄
膜トランジスタの断面構造を示す図である。
FIG. 3 is a diagram showing a cross-sectional structure of a conventional top-gate staggered a-Si thin film transistor.

1は絶縁基板であり、その上に間隔をおいて、ソース電
極Sとドレイン電極りが1000人程度0厚さに形成さ
れ、両電極の上にオーミックコンタクト層2s、 2d
が300〜500人程度積層されている。そしてその上
にa−Siから成る活性N3を1000人程度0厚−ト
絶縁膜4を1000〜1500人程度成膜し、最後にゲ
ート電極Gを成膜した構造になっている。
Reference numeral 1 denotes an insulating substrate, on which a source electrode S and a drain electrode are formed with a thickness of about 1,000 at intervals, and ohmic contact layers 2s and 2d are formed on both electrodes.
There are about 300 to 500 people stacked up. Then, a zero-thickness insulating film 4 of about 1,000 to 1,500 people was formed to form an active N3 layer made of a-Si by about 1,000 people, and finally a gate electrode G was formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところがこのような断面構造では、ソース・ドレイン電
極とオーミックコンタクト層の合計膜厚が1300〜1
500程度となり、絶縁基板1との間の段差が大きくな
るので、その上に成膜されたa−3t活性層2およびゲ
ート絶縁膜3にも段差部ができる。
However, in such a cross-sectional structure, the total thickness of the source/drain electrode and the ohmic contact layer is 1300~1.
500, and the difference in level between the insulating substrate 1 and the insulating substrate 1 becomes large, so that the a-3t active layer 2 and the gate insulating film 3 formed thereon also have a step part.

そのため、a−3i活性層3の段差部に亀裂が入ったり
、肋膜が生じるおれがあり、特性の安定性が悪いという
欠点がある。
As a result, the a-3i active layer 3 has cracks in the stepped portion and plenum formation, resulting in poor stability of properties.

本発明の技術的課題は、従来のa−3iFI膜トランジ
スタにおけるこのような問題を解消するために、a−S
i活性層3に段差が生じない構造とすることにある。
The technical problem of the present invention is to solve such problems in the conventional a-3i FI film transistor.
The purpose is to create a structure in which no step occurs in the i-active layer 3.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明によるa−3il膜トランジスタの基本
原理を説明する断面図である。絶縁基板1上に、ソース
電極Sとドレイン電極りが形成されているが、両電極S
、D間の凹部には、無機薄膜5を埋めた構造になってい
る。そしてこれらの上にa−3i活性層3、ゲート絶縁
膜4の順に積層され、その上にゲートGが形成されてい
る。なおソース電極Sとドレイン電極り上に、オーミッ
クコンタクト層を設ける場合は、該オーミックコンタク
ト層と無機薄膜5の面が、同じ高さに揃うようにする。
FIG. 1 is a sectional view illustrating the basic principle of an A-3IL film transistor according to the present invention. A source electrode S and a drain electrode are formed on the insulating substrate 1.
, D has a structure in which an inorganic thin film 5 is buried in the recess. Then, an a-3i active layer 3 and a gate insulating film 4 are laminated in this order on these, and a gate G is formed thereon. Note that when an ohmic contact layer is provided on the source electrode S and the drain electrode, the surfaces of the ohmic contact layer and the inorganic thin film 5 are made to be at the same height.

〔作用〕[Effect]

このように、ソース電極Sとドレイン電極り間の凹部が
無機薄膜5で埋められ、a−3i活性層3の下面がプレ
ーナ化されるので、a−3i活性層3およびゲート絶縁
膜4に段差が発生しない。そのため、a−3i活性層3
に亀裂や肋膜などが発生する恐れはなく、特性が安定し
、信頼性が向上する。
In this way, the recess between the source electrode S and the drain electrode is filled with the inorganic thin film 5, and the lower surface of the a-3i active layer 3 is planarized, so that there is no step difference in the a-3i active layer 3 and the gate insulating film 4. does not occur. Therefore, a-3i active layer 3
There is no risk of cracks or plenums occurring, resulting in stable characteristics and improved reliability.

〔実施例〕〔Example〕

次に本発明によるa−3iFI膜トランジスタが実際上
どのように具体化されるかを実施例で説明する。
Next, how the a-3i FI film transistor according to the present invention is actually implemented will be explained using examples.

第2図は本発明によるa−3il膜トランジスタの実施
例、および同実施例装置の製造方法を工程順に示す断面
図である。この実施例は、(f)に示すように、絶縁基
板1上の、ソース電極Sとドレイン電極りとの間に、無
機薄膜5を設け、ソース・ドレイン電極S、D上のオー
ミンクコンタクト層2s。
FIG. 2 is a cross-sectional view showing an embodiment of an A-3IL film transistor according to the present invention and a method of manufacturing the device of the embodiment in the order of steps. In this embodiment, as shown in (f), an inorganic thin film 5 is provided between a source electrode S and a drain electrode on an insulating substrate 1, and an ohmink contact layer is formed on the source and drain electrodes S and D. 2s.

2dの面と無機薄膜5の面とが同一面に揃うようになっ
ている。こうしてプレーナ化された面上に、a−3i活
性層3、ゲート絶縁膜4の順に成膜され、最上部にゲー
トGが形成されている。
The surface 2d and the surface of the inorganic thin film 5 are arranged on the same plane. On the thus planarized surface, an a-3i active layer 3 and a gate insulating film 4 are formed in this order, and a gate G is formed at the top.

この装置において、ドレイン電圧を一定にした状態で、
ゲート電圧を変えると、ある点でゲート電圧の増加に伴
って急激にドレイン電流が増加する特性を示し、スイッ
チング機能が得られる。なおドレイン電流は、ソース電
極S−オーミックコンタクト層2s −a−3i活性層
3−オーミックコンタクト層2d−ドレイン電極りの経
路を流れる。
In this device, with the drain voltage constant,
When the gate voltage is changed, the drain current exhibits a characteristic in which the drain current increases rapidly at a certain point as the gate voltage increases, providing a switching function. Note that the drain current flows through the path of source electrode S-ohmic contact layer 2s-a-3i active layer 3-ohmic contact layer 2d-drain electrode.

次にこの実施例装置の製造方法を工程順に説明する。ま
ずfatのように、絶縁基板1上に、グロー放電分解法
などを用いて、無機薄膜5aを全面に成膜する。この無
8!薄膜5aとしては、a−3ts S+0□、SiN
、SiC,a−Cなどが適している。次に(blのよう
に、ソース・ドレイン電極S、Dの反転形状のレジスト
マスク6を形成し、ソース電極Sおよびドレイン電極り
部分の無機薄膜をエツチング除去して、凹部7a、7b
を形成する。次いで(C1のように、レジストマスク6
の上から、TI%旧Cr、 Cr、 AI等のソース・
ドレイン電極材を真空蒸着し、続いてn +a−3i等
のグロー放電分解法によりオーミックコンタクト層2を
成膜する。そしてレジストマスク6を除去することで、
余分な部分をリフトオフし、(dlのようにプレーナ化
する。次いでa−Si活性層3 、SiN、 SiO□
等から成るゲート絶縁膜4を連続的に成膜し、バターニ
ング・エツチングし、余分の領域を除去して+elの構
成とする。最後に、NiCr、 AI、Mo、 Crな
どを蒸着しパターニングすることにより、ゲートGを形
成することで、(flのようなトップ・ゲート・スタガ
型の薄膜トランジスタが完成する。
Next, the manufacturing method of this example device will be explained step by step. First, like fat, an inorganic thin film 5a is formed on the entire surface of the insulating substrate 1 using a glow discharge decomposition method or the like. This nothingness 8! As the thin film 5a, a-3ts S+0□, SiN
, SiC, a-C, etc. are suitable. Next, as shown in (bl), a resist mask 6 with an inverted shape of the source/drain electrodes S and D is formed, and the inorganic thin film on the source electrode S and drain electrode portion is removed by etching.
form. Then (as in C1, resist mask 6
From above, sources such as TI% old Cr, Cr, AI, etc.
A drain electrode material is vacuum deposited, and then an ohmic contact layer 2 is formed by a glow discharge decomposition method such as n+a-3i. And by removing the resist mask 6,
The excess portion is lifted off and planarized as shown in (dl). Then, the a-Si active layer 3, SiN, SiO□
A gate insulating film 4 consisting of the above is continuously formed, patterned and etched, and the excess region is removed to form a +el structure. Finally, a gate G is formed by depositing and patterning NiCr, AI, Mo, Cr, etc., thereby completing a top-gate staggered thin film transistor such as (fl).

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、a−Si活性層の下面が
平坦となるため、a−3i活性層およびゲート絶縁膜に
凹凸ができず、膜の亀裂や肋膜が発生しない。その結果
、特性が安定した、信頼性の高いa−3i薄膜トランジ
スタを実現できる。
As described above, according to the present invention, since the lower surface of the a-Si active layer is flat, unevenness does not occur in the a-3i active layer and the gate insulating film, and film cracks and linings do not occur. As a result, a highly reliable a-3i thin film transistor with stable characteristics can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるa−Sifi膜トランジスタの基
本原理を説明する断面図、第2図は本発明の実施例装置
とその製造方法を工程順に示す断面図、第3図は従来の
a−3i薄膜トランジスタを示す断面図である。 図において、Sはソース電極、Dはドレイン電極、2s
、2dはオーミックコンタクト層、3はa−Si活性層
、4はゲート絶縁膜、Gはゲートをそれぞれ示す。 特許出願人     富士通株式会社 代理人 弁理士   青 柳   稔 第1図 1の41− s i 簿# )ラシジ又り第3図 無機導膜 5δ (C) 実施例と製法 第2図 (fン
FIG. 1 is a cross-sectional view explaining the basic principle of an a-Sifi film transistor according to the present invention, FIG. FIG. 3 is a cross-sectional view showing a 3i thin film transistor. In the figure, S is the source electrode, D is the drain electrode, 2s
, 2d is an ohmic contact layer, 3 is an a-Si active layer, 4 is a gate insulating film, and G is a gate. Patent Applicant: Fujitsu Limited Agent, Patent Attorney Minoru Aoyagi (Figure 1) 41-s i Book #) Lasijimata Figure 3 Inorganic conductive film 5δ (C) Examples and manufacturing process Figure 2 (fn)

Claims (1)

【特許請求の範囲】 ソース電極とドレイン電極が絶縁基板側に配置されるト
ップ・ゲート・スタガ型a−Si薄膜トランジスタにお
いて、 ソース電極(S)とドレイン電極(D)との間の凹部に
無機薄膜(5)を設けることで、a−Si活性層(3)
が平坦となるようにしたことを特徴とするa−Si薄膜
トランジスタ。
[Claims] In a top-gate staggered a-Si thin film transistor in which the source electrode and drain electrode are arranged on the insulating substrate side, an inorganic thin film is formed in the recess between the source electrode (S) and the drain electrode (D). By providing (5), the a-Si active layer (3)
1. An a-Si thin film transistor characterized by having a flat surface.
JP61060047A 1986-03-18 1986-03-18 A-si thin film transistor Pending JPS62216372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61060047A JPS62216372A (en) 1986-03-18 1986-03-18 A-si thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61060047A JPS62216372A (en) 1986-03-18 1986-03-18 A-si thin film transistor

Publications (1)

Publication Number Publication Date
JPS62216372A true JPS62216372A (en) 1987-09-22

Family

ID=13130775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61060047A Pending JPS62216372A (en) 1986-03-18 1986-03-18 A-si thin film transistor

Country Status (1)

Country Link
JP (1) JPS62216372A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342909A (en) * 1990-08-29 1994-12-13 Internatl Business Mach Corp <Ibm> Thin-film transistor and its manufacture
JP2011222736A (en) * 2010-04-09 2011-11-04 Semiconductor Energy Lab Co Ltd Semiconductor device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54141581A (en) * 1978-04-26 1979-11-02 Matsushita Electric Ind Co Ltd Thin film transistor
JPS5721867A (en) * 1980-06-02 1982-02-04 Xerox Corp Planar thin film transistor array and method of producing same
JPS6184066A (en) * 1984-10-01 1986-04-28 Oki Electric Ind Co Ltd Manufacturing method of thin film transistor
JPS61201469A (en) * 1985-03-05 1986-09-06 Oki Electric Ind Co Ltd Thin film transistor and its manufacturing method
JPS61204976A (en) * 1985-03-08 1986-09-11 Seiko Instr & Electronics Ltd Thin film transistor device and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54141581A (en) * 1978-04-26 1979-11-02 Matsushita Electric Ind Co Ltd Thin film transistor
JPS5721867A (en) * 1980-06-02 1982-02-04 Xerox Corp Planar thin film transistor array and method of producing same
JPS6184066A (en) * 1984-10-01 1986-04-28 Oki Electric Ind Co Ltd Manufacturing method of thin film transistor
JPS61201469A (en) * 1985-03-05 1986-09-06 Oki Electric Ind Co Ltd Thin film transistor and its manufacturing method
JPS61204976A (en) * 1985-03-08 1986-09-11 Seiko Instr & Electronics Ltd Thin film transistor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342909A (en) * 1990-08-29 1994-12-13 Internatl Business Mach Corp <Ibm> Thin-film transistor and its manufacture
JP2011222736A (en) * 2010-04-09 2011-11-04 Semiconductor Energy Lab Co Ltd Semiconductor device and method for manufacturing the same

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