JPS6178166A - Thin film transistor array and its manufacturing method - Google Patents
Thin film transistor array and its manufacturing methodInfo
- Publication number
- JPS6178166A JPS6178166A JP59200006A JP20000684A JPS6178166A JP S6178166 A JPS6178166 A JP S6178166A JP 59200006 A JP59200006 A JP 59200006A JP 20000684 A JP20000684 A JP 20000684A JP S6178166 A JPS6178166 A JP S6178166A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- gate electrode
- film transistor
- transistor array
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010409 thin film Substances 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 14
- 239000012212 insulator Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000010408 film Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 239000000615 nonconductor Substances 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6746—Amorphous silicon
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶表示用アクティブマトリックススイッチ
ングアレーとその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix switching array for liquid crystal displays and a method for manufacturing the same.
従来例の構成とその問題点
液晶表示用アクティブマトリックスアレーは、フラット
表示パネル、ポータプルＴ、 Ｖ、等の目的のために精
力的に開発され、市場に少しずつ出ようとしている。現
在アクティブ素子として、非晶質シリコン（以下ａ−３
ｉと略す）あるいはポリノリコン等が使用され１第１図
に示すように、ゲート電険２が下側にある逆スタツガ−
型薄膜トランジスター（以下Ｔ、Ｆ、Ｔと略す）と、第
２図に示すようにソース、ドレイン電極５が下側にある
スタ７ガー型ＴＰＴが開発されている。両タイプとも実
用化されつ・りあるが、スタッガー型ＴＰＴの液晶表示
用アクティブマトリックスアレーの断面図の一部の従来
例を第３図ａ、ｂに示し、その構成と欠点を以下に説明
する。Conventional configurations and their problems Active matrix arrays for liquid crystal displays have been vigorously developed for purposes such as flat display panels, portable T, V, etc., and are gradually coming onto the market. Currently, amorphous silicon (hereinafter referred to as a-3) is used as an active element.
(abbreviated as "i") or a poly-container or the like is used.1 As shown in Fig.
Type thin film transistors (hereinafter abbreviated as T, F, and T) and staggered type TPTs in which the source and drain electrodes 5 are on the lower side as shown in FIG. 2 have been developed. Although both types are on the verge of being put into practical use, a cross-sectional view of a part of a conventional example of an active matrix array for a staggered TPT liquid crystal display is shown in Figures 3a and b, and its structure and drawbacks are explained below. .
第３図ａ、ｂとも、透明絶縁基板１上にソース７１ｉ５
、ドレイン電極および絵素電極５′が形成キｔｔてち・
す、その上にａ−３工等の非晶質半導体４がアクティブ
層として、ゲート絶縁体層３としてのンリコンナイトラ
イド（以上ＳｉＮｘと略す）等がパターニング形成され
ている。さらにその上に、ゲート電極３が設けられ、表
示−絵素の等価回路（第４図）のスイッチング素子部６
を構成する。In both FIGS. 3a and 3b, the source 71i5 is placed on the transparent insulating substrate 1.
, the drain electrode and the picture element electrode 5' are formed.
Thereon, an amorphous semiconductor 4 such as A-3 is formed as an active layer, and a gate insulator layer 3 such as silicon nitride (hereinafter abbreviated as SiNx) is formed by patterning. Furthermore, a gate electrode 3 is provided thereon, and a switching element section 6 of the display-picture element equivalent circuit (FIG. 4) is provided.
Configure.
第３図ａ、ｂで示した従来例で、パターニングに必要な
マスクの枚数は、ゲート電極パターニング用、半導体層
および絶縁体層のパターニング用、さらにゲート電極パ
ターニング用と、最低でも４枚である。表示面積が拡大
化し、パターン精度が上がると、マスク枚数の増化は歩
留りの低下、パターンずれ等の問題が生じさせる。In the conventional example shown in FIGS. 3a and 3b, the number of masks required for patterning is at least four: one for patterning the gate electrode, one for patterning the semiconductor layer and the insulator layer, and one for patterning the gate electrode. . As the display area increases and pattern accuracy increases, the increase in the number of masks causes problems such as a decrease in yield and pattern deviation.
発明の目的
発明の目的は、ＴＰＴスイノチノグアレーのマスク枚数
を減らして歩留りの向上をはかるための薄膜トランジス
ターアレーとその製造方法を提供するもの・である。OBJECTS OF THE INVENTION An object of the invention is to provide a thin film transistor array and its manufacturing method for reducing the number of masks in a TPT Suinochinoga array and improving yield.
発明の構成
本発明の薄膜トランジスターアレーの構造とその製造方
法は、透明絶縁基板上にソース、ドレイン電極、非晶質
半導体層、絶縁体層、およびゲート電極を順に形成した
スタッガー型薄膜トランジスターアレーに関して、ゲー
ト電極と同一形状にゲート電極をマスクにして絶縁体層
と非晶質半導体層をパターニングする構造、製造法を提
供し、それによって、マスク枚数の低減下が出来１歩留
りの向上をはかることが可能となる。Structure of the Invention The structure of the thin film transistor array and the manufacturing method thereof of the present invention relate to a staggered thin film transistor array in which a source, a drain electrode, an amorphous semiconductor layer, an insulator layer, and a gate electrode are sequentially formed on a transparent insulating substrate. To provide a structure and manufacturing method for patterning an insulator layer and an amorphous semiconductor layer using the gate electrode as a mask in the same shape as the gate electrode, thereby reducing the number of masks and improving yield. becomes possible.
実施例の説明
本発明の実施例の断面図を第６図ａ、ｂに平面図を第５
図Ｇに示す。絶縁基板上１にソース？１１．極５、゛
−ドレイン電極および絵素電極５′上に、ゲ
ート電極２と同一形状にゲート絶縁体層３と半導体層４
をパターニング形成した構成を有する。第５図ａはソー
ス、ドレイン電極上にｎ士卒導体層９を付けない場合で
あり第５図すはｎ＋層９を有する場合であ乙。その製造
工程を第６図＆−６で説明する。第１の工程で透明絶縁
基板１上にソース電極５、ドレイン絵素電極５′をパタ
ーニングする。第２の工程で、上記第１の工程で得られ
た基板上に、プラズマＣＶＤ法によりａ−３ｉ、ＳｉＮ
を真空を破らず連続的に形成す己。次に第３の工程
で、ゲート電（仮のだめのノタルを蒸着した断面図を第
６図ａに示す。さらに第３の工程で、ゲートパターン用
のレジスト８をフォトレジストで形成し、それをマスク
にして。DESCRIPTION OF THE EMBODIMENTS The cross-sectional view of the embodiment of the present invention is shown in FIGS. 6a and 6b, and the plan view is shown in FIG.
Shown in Figure G. Source on insulation board 1? 11. Extreme 5,゛
- On the drain electrode and the picture element electrode 5', a gate insulator layer 3 and a semiconductor layer 4 are formed in the same shape as the gate electrode 2.
It has a structure formed by patterning. 5a shows the case where the n+ conductor layer 9 is not provided on the source and drain electrodes, and FIG. 5a shows the case where the n+ layer 9 is provided. The manufacturing process will be explained with reference to FIGS. In the first step, a source electrode 5 and a drain pixel electrode 5' are patterned on the transparent insulating substrate 1. In the second step, on the substrate obtained in the first step, a-3i, SiN
The self that continuously forms without breaking the vacuum. Next, in the third step, a cross-sectional view of the gate electrode (temporary gate electrode) deposited is shown in FIG. Make it a mask.
第６図すの様に、ゲート電極２を形成する。最終の第４
の工程では、第３の工程でパターニングしたレジスト８
とゲート’ｌ極２をマスクにして。As shown in FIG. 6, a gate electrode 2 is formed. the fourth and final
In the step, the resist 8 patterned in the third step
and gate'l pole 2 as a mask.
５ｌＮｘ層３およびａ−５１層４を１ノチ／グする。Cut 51Nx layer 3 and a-51 layer 4 one notch.
レジストを除去して、第５図ａ、ｃに示すような液晶表
示用ＴＦＴマトリックススイッチングアレーを形成する
。The resist is removed to form a TFT matrix switching array for liquid crystal display as shown in FIGS. 5a and 5c.
ソース、ドレ・ｆン′屯琢上にｎ＋半導体層を形成する
第５図すの構造を有するＴＰＴの製造方法を以下に説明
する。A method of manufacturing a TPT having the structure shown in FIG. 5, in which an n+ semiconductor layer is formed on the source and drain layers, will be described below.
第６図ｄに示すようにソース、トンイン電極用金民をス
パッターあるいは蒸着により形成した基板上に、ｐ−ｃ
ｖｐ法により１半導体層を成膜する。As shown in FIG. 6d, p-c
One semiconductor layer is formed by the vp method.
次に第６図ｅに示すように、通常のフォトリソグラフィ
を用いでｎ＋層ｅ、および蒸着金属９を所定の形状にパ
ターニングする。第６図Ｃの基板を用いて１第６図ａ、
ｂ、ｃの工程を経て、第５図すの構造を有するＴＰＴア
レーを形成する。Next, as shown in FIG. 6e, the n+ layer e and the deposited metal 9 are patterned into a predetermined shape using normal photolithography. Using the board of FIG. 6C, 1 FIG. 6a,
Through steps b and c, a TPT array having the structure shown in FIG. 5 is formed.
ＴＰＴ構造の一例として１表１の様な構成を考える。Consider a configuration as shown in Table 1 as an example of a TPT structure.
表１
各層の選択エツチングに対し、Ｃｒのエッチャントは、
ＳｉＮｘを陵しよくしないし、Ｓ工Ｎｘのエッチャント
のＢ）ｆＦ（ＩＦ液とＮＨ，Ｆの混液）Ｋ対し、Ｃｒは
上にレジストを残したままだと問題ない。さらに＞−３
ｉのエツチノグをＮａＯＨを使用すれば、 ｎ＋１−
ｓｉも同時にエツチング出来しかもＩＴＯを含め、他の
各層をおかさずに、バターニングできる。したがって、
ソースドレイン電極をパターニングするマスクと、ゲー
ト電極をパターニングするマスクの２枚で透過型液晶表
示用ＴＰＴスイ、テングマレーを構成することが出来る
。Table 1 For selective etching of each layer, Cr etchant is
It does not damage the SiNx, and unlike the S-Nx etchant B)fF (a mixture of IF liquid, NH, and F), Cr does not cause any problems if the resist is left on top. Furthermore >-3
If you use NaOH for Etsuchinog of i, n+1-
Si can also be etched at the same time, and it can be buttered without damaging other layers, including ITO. therefore,
A TPT switch for a transmissive liquid crystal display and a tengumarray can be constructed using two masks: a mask for patterning source/drain electrodes and a mask for patterning gate electrodes.
発明の効果
第５図ａ、ｂに示すような、ゲート電極２をマスクにし
てゲート１Ｔ：、極と同一形状にゲート絶縁体層３と非
晶質半導体２をバターニングしたＴＰＴ構成をとれば、
フォトレジストによるバターニングエパにおいて、マス
クが２枚に減少できるという効果をもつことになる。こ
れＫより、ＴＦＴアレーの欠陥が減り歩留りの向上が出
来る。Effects of the Invention If a TPT structure is adopted in which the gate insulator layer 3 and the amorphous semiconductor 2 are patterned in the same shape as the gate 1T: and the pole using the gate electrode 2 as a mask, as shown in FIGS. 5a and 5b, ,
This has the effect that the number of masks can be reduced to two in the patterning process using photoresist. With K, defects in the TFT array can be reduced and the yield can be improved.
第１図は、ゲート電極が下側にある逆スタツガ−型ＴＰ
Ｔの断面１２、第２図、第３図＆、ｂは、ゲート電極が
上側にある従来のスタッガー型ＴＰＴの断面図、第４図
は液晶表示用ＴＰＴマトリックススイッチングアレーの
一絵素の等価回路図、第５図へは本発明によるＴＰＴマ
トリックススイッチングアレーの一絵素分の断面図、第
５図すは第５図＆でソースドレイン電極上にｎ＋半導体
層を有する場合の断面図、第５図Ｃは第５図ａ、ｂの平
面図、第６図ａ、ｂ、ｃは本発明の第６図ａのＴＰＴア
レーを製造する工程口、第６図ｄ、ｅは第６図すのため
に付加される工程図である。
１・・・・透明絶縁基板、２・・・・・ゲート電極、３
・・・ゲート絶縁体層、４・・・・非晶質半導体層、５
・・・・・ソースＴＬ葎、ｓ’ ・・・・・ドレインお
よび絵素電画。
６・・・・・液晶表示用ＴＰＴスイッチング部、７・・
・・・液晶表示用絵素部、８・・・・・ゲート電極をバ
ターニングするためのレジスト、９・・・・ソース、ド
レインｍｆｆ１上に形成したｎ＋半導体層である。
代理人の氏名 弁理士 中 尾 赦 男 ほか１８筒１
図
案 ４ 図
升峨］
第 ５ 図
第 ６ 図
？
第６図Figure 1 shows an inverted staggered TP with the gate electrode on the bottom.
Cross section 12 of T, Figures 2, 3 & b are cross-sectional views of a conventional staggered TPT with the gate electrode on the upper side, and Figure 4 is an equivalent circuit of one pixel of a TPT matrix switching array for liquid crystal display. 5 is a cross-sectional view of one pixel element of a TPT matrix switching array according to the present invention, and FIG. Figure C is a plan view of Figures 5a and 5b, Figures 6a, b, and c are process steps for manufacturing the TPT array of Figure 6a of the present invention, and Figures 6d and e are the same as Figure 6. It is a process diagram added for this purpose. 1...Transparent insulating substrate, 2...Gate electrode, 3
...gate insulator layer, 4...amorphous semiconductor layer, 5
... Source TL, s' ... Drain and picture element electric picture. 6... TPT switching section for liquid crystal display, 7...
. . . Picture element portion for liquid crystal display, 8 . . . Resist for patterning the gate electrode, 9 . . . N+ semiconductor layer formed on the source and drain mff1. Name of agent: Patent attorney Masao Nakao and 18 others 1
Design 4 Figure 6 Figure 5? Figure 6
Claims (4)
質半導体層、絶縁体層、およびゲート電極を順に形成し
たスタッガー型薄膜トランジスターアレーに関して、前
記ゲート電極と同一形状に絶縁体層と非晶質半導体層が
パターニングされた構造を有すること特徴とする薄膜ト
ランジスターアレー。(1) Regarding a staggered thin film transistor array in which a source, a drain electrode, an amorphous semiconductor layer, an insulator layer, and a gate electrode are sequentially formed on a transparent insulating substrate, an insulator layer and a non-conductor are formed in the same shape as the gate electrode. A thin film transistor array characterized by having a structure in which a crystalline semiconductor layer is patterned.
＋非晶質半導体層が、ソース、ドレイン電極と同一形状
にパターニングされた構造を特徴とする特許請求の範囲
第１項記載の薄膜トランジスターアレー。(2) n^ on the source and drain electrodes on the transparent insulating substrate
+The thin film transistor array according to claim 1, characterized in that the amorphous semiconductor layer is patterned in the same shape as the source and drain electrodes.
る第１の工程、プラズマＣＶＤ法で非晶質半導体層、絶
縁体層を真空を破らず連続して成膜する第２の工程、前
記第２の工程で準備された基板上にゲート電極を蒸着、
パターニングする第３の工程、最後に前記第３の工程で
パターニングしたゲート電極をマスクにして、絶縁体層
、非晶質半導体層をゲート電極と同一形状にパターニン
グする第４の工程を含むことを特徴とする薄膜トランジ
スターアレーの製造方法。(3) a first step of forming source and drain electrodes on a transparent insulating substrate; a second step of continuously forming an amorphous semiconductor layer and an insulating layer without breaking the vacuum by plasma CVD; Depositing a gate electrode on the substrate prepared in the second step,
A third step of patterning, and finally a fourth step of patterning the insulator layer and the amorphous semiconductor layer in the same shape as the gate electrode using the gate electrode patterned in the third step as a mask. A method for manufacturing a featured thin film transistor array.
スパッターあるいは蒸着で付け、その上にｎ＾＋非晶質
シリコンをプラズマＣＶＤ法で成膜し、通常のフォトリ
ソグラフィを用いて、所定の形状にｎ＾＋非晶質シリコ
ン、蒸着金属をエッチングパターニング形成する第１の
工程を含む、特許請求の範囲第３項記載の薄膜トランジ
スターアレーの製造方法。(4) Source and drain electrode metals are attached on a transparent insulating substrate by sputtering or vapor deposition, a film of n^+ amorphous silicon is formed on top of the metal by plasma CVD, and a predetermined pattern is formed using ordinary photolithography. 4. The method for manufacturing a thin film transistor array according to claim 3, comprising a first step of etching and patterning n^+ amorphous silicon and vapor deposited metal in the shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200006A JPS6178166A (en) | 1984-09-25 | 1984-09-25 | Thin film transistor array and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200006A JPS6178166A (en) | 1984-09-25 | 1984-09-25 | Thin film transistor array and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6178166A true JPS6178166A (en) | 1986-04-21 |
Family
ID=16417223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59200006A Pending JPS6178166A (en) | 1984-09-25 | 1984-09-25 | Thin film transistor array and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6178166A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6446982A (en) * | 1987-08-17 | 1989-02-21 | Casio Computer Co Ltd | Manufacture of thin-film transistor |
| JPH01253964A (en) * | 1988-04-01 | 1989-10-11 | Nec Corp | Thin film field effect transistor element array and its manufacture |
| US5691782A (en) * | 1994-07-08 | 1997-11-25 | Sanyo Electric Co., Ltd. | Liquid-crystal display with inter-line short-circuit preventive function and process for producing same |
| KR100268299B1 (en) * | 1996-09-06 | 2000-10-16 | 구본준 | Stagger type thin-film transistor with iop structure |
| JP2007036247A (en) * | 2005-07-28 | 2007-02-08 | Palo Alto Research Center Inc | Electrical component manufacturing method and electrical component structure |
| JP2007150240A (en) * | 2005-11-29 | 2007-06-14 | Lg Philips Lcd Co Ltd | THIN FILM TRANSISTOR AND ITS MANUFACTURING METHOD, ARRAY SUBSTRATE PROVIDED WITH THIN FILM TRANSISTOR AND ITS MANUFACTURING METHOD |
| US8497494B2 (en) * | 2006-11-24 | 2013-07-30 | Lg Display Co., Ltd. | Thin film transistor and array substrate for liquid crystal display device comprising organic insulating material |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114458A (en) * | 1981-12-23 | 1983-07-07 | フラスワ・モリン | Method of producing thin film transistor on insulating substrate |
| JPS59232385A (en) * | 1983-06-15 | 1984-12-27 | 株式会社東芝 | Active matrix type display unit |
-
1984
- 1984-09-25 JP JP59200006A patent/JPS6178166A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114458A (en) * | 1981-12-23 | 1983-07-07 | フラスワ・モリン | Method of producing thin film transistor on insulating substrate |
| JPS59232385A (en) * | 1983-06-15 | 1984-12-27 | 株式会社東芝 | Active matrix type display unit |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6446982A (en) * | 1987-08-17 | 1989-02-21 | Casio Computer Co Ltd | Manufacture of thin-film transistor |
| JPH01253964A (en) * | 1988-04-01 | 1989-10-11 | Nec Corp | Thin film field effect transistor element array and its manufacture |
| US5691782A (en) * | 1994-07-08 | 1997-11-25 | Sanyo Electric Co., Ltd. | Liquid-crystal display with inter-line short-circuit preventive function and process for producing same |
| KR100268299B1 (en) * | 1996-09-06 | 2000-10-16 | 구본준 | Stagger type thin-film transistor with iop structure |
| JP2007036247A (en) * | 2005-07-28 | 2007-02-08 | Palo Alto Research Center Inc | Electrical component manufacturing method and electrical component structure |
| JP2007150240A (en) * | 2005-11-29 | 2007-06-14 | Lg Philips Lcd Co Ltd | THIN FILM TRANSISTOR AND ITS MANUFACTURING METHOD, ARRAY SUBSTRATE PROVIDED WITH THIN FILM TRANSISTOR AND ITS MANUFACTURING METHOD |
| JP4676390B2 (en) * | 2005-11-29 | 2011-04-27 | エルジー ディスプレイ カンパニー リミテッド | Thin film transistor and manufacturing method thereof |
| US8716696B2 (en) | 2005-11-29 | 2014-05-06 | Lg Display Co., Ltd. | Organic semiconductor thin film transistor and method of fabricating the same |
| US9178169B2 (en) | 2005-11-29 | 2015-11-03 | Lg Display Co., Ltd. | Organic semiconductor thin film transistor and method of fabricating the same |
| US9496511B2 (en) | 2005-11-29 | 2016-11-15 | Lg Display Co., Ltd. | Organic semiconductor thin film transistor and method of fabricating the same |
| US8497494B2 (en) * | 2006-11-24 | 2013-07-30 | Lg Display Co., Ltd. | Thin film transistor and array substrate for liquid crystal display device comprising organic insulating material |
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