JPS61137370A - Manufacturing method of MOS semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a MOS semiconductor device, and more particularly to a method for manufacturing a MOS semiconductor device having a double insulating film structure.

[Technical background of the invention] For example, MA
O8 type upper gate structure tal-AI 203-8i
The MO3 semiconductor device with this structure has two insulating films (AI 203 and S + 02).
Because it is possible to effectively utilize the negative charge generated at the interface of 5in219! N-channel enhancement type MOS, which was difficult to realize with MO3 semiconductor devices that only have
A semiconductor device can be easily manufactured.

Conventionally, when manufacturing a MOS semiconductor device with a MAO3 type O3 structure, A1□0. CVD as a method of forming a film
method, PVD method, AI film oxidation method, etc. For example, as a CVD method for forming A1□o3m, there is a method in which ■Al cl and CO2 are reacted at 900°C, and ■A method in which an organic compound t' of A1 is reacted with a certain AI (CO
3H,), and AI(CO2H,), etc.e 400'C
Methods of thermal decomposition of IIR are known, and PV
As the D method, two methods are known: (1) performing high-frequency sputtering using A I 203 as a target, and (2) performing reactive sputtering in an oxygen atmosphere using A1 as a target. On the other hand, as the A1 film oxidation method, there are two methods: (1) using an aqueous solution, and (2) a method using oxygen plasma.

[Problems in the Background Art] With the conventional alumina film forming method as described above, it is difficult to achieve uniform film thickness and uniform film quality over the entire wafer surface. There was a problem that the performance of the elements was not uniform.

In particular, in recent years, MOS semiconductor devices have become faster and more highly integrated, and wafers are also becoming larger in diameter. However, in the case of semiconductor devices with MAO8 structure, as mentioned above, the conventional alumina film formation method cannot form a uniform film over the entire wafer surface, so it is necessary to increase the diameter of the wafer. As devices become more highly integrated, there is a risk that device yields will drop even further than they currently do.

[Objective of the Invention] The object of the present invention is to realize the formation of a highly accurate metal oxide film with uniform film quality and thickness, thereby producing a double insulating film type MO3 semiconductor device with uniform performance at a high yield. An object of the present invention is to provide a method for manufacturing a TFR standard semiconductor device.

[Summary of the Invention 1 This invention method uses ion implantation, which has excellent uniformity of film quality and thickness, controllability of film formation, and mass productivity, as a means for forming thin films of metal oxides such as Al2O3 with high precision. By adopting the ion implantation method and preventing the occurrence of element deterioration phenomena caused by the adoption of the ion implantation method, we have developed an MO3 semiconductor with a double insulating film structure equipped with a highly precise metal oxide film with uniform film quality and thickness. It is characterized by manufacturing a device.

Generally, when metal atoms such as A1 are ion-implanted into 5i02, 2Al+2SiO2 → A1□Os + Si O+ is formed in 5i02 during the invasive heat treatment process.
8 + reaction occurs and suboxide silicon SiO and free silicon Si are produced. This free silicon acts as a mobile ion, and silicon suboxide acts as an unstable ion, leading to deterioration of gate breakdown voltage in MOS structure elements, but the method of the present invention prevents such phenomena from occurring. In order to achieve this, the mechanism is to convert unstable ions such as SiO and 3i into stable 5i02 by ion-implanting oxygen atoms together with metal atoms. That is, in the method of the present invention, after ion-implanting metal atoms such as A1 and oxygen atoms into the surface layer of a silicon thermal oxide film, a thin metal oxide layer is formed on the silicon thermal oxide layer by heat-treating the ion-implanted portion. At the same time as the silicon thermal oxide film is formed, free S: and silicon suboxide (SiO) in the silicon thermal oxide film are oxidized to 5i02 by oxygen injected into the silicon thermal oxide film to make it physically and chemically stable.

In addition to A I 203, Ti 02 and Ta 2
03, WO2, Zr 02 , Hf 02 , Pb O
A MOS semiconductor device having the same double insulating film structure as the MAO8 structure can be constructed using various metal oxide layers such as Ti, Ta, W, Zr, Hr, etc.
pb can also be used in place of A1 in the method of the invention.

The amount of ion implantation of oxygen atoms may be equivalent to that of metal atoms, but it is better to have a slight excess.

[Embodiment of the Invention] An embodiment of the method of the present invention will be described below with reference to FIG. 1 of the accompanying drawings.

Prior to carrying out the method of the present invention, first, a semiconductor substrate 1 of a P-type low concentration layer on which a channel cut region 1A consisting of a P-type high concentration layer is formed as shown in FIG. 1(a) is prepared.
Here, reference numeral 2 denotes a field oxide film, and a region where a channel is to be formed is exposed as an opening 2a.

Next, as shown in FIG. 1(b), a gate oxide film 3 (thermal oxide film) with a thickness of 1200× is formed on the surface of the semiconductor substrate 1 exposed in the opening 2a, and then as shown in FIG. 1(C). As shown by arrows, A1 and oxygen are ion-implanted into the gate oxide 113 and the surrounding thermal oxidation layer 12. In this case, the acceleration voltage and dose ω are determined to appropriate values so that the implanted ions remain on the surface layer of the gate oxide 113 (for example, for AI, the acceleration voltage is 20 keV and the dose is 3X 10").
2. Oxygen has an accelerating voltage of 30 keV and a dose of 5x.
10” cr2).

After that, heat treatment is performed at 1000°C for 10 minutes in a nitrogen atmosphere, and gate oxidation occurs as shown in Figure 1(d).
113 and field oxidation on the surface of 1 m2 with a thickness of about 400
A thin layer of Al2O5 is formed. In this case, as mentioned above, A1
Free 3i and SiO are not generated because an excessive amount of oxygen is ion-implanted. In addition, since the implantation depth and distribution of A1 can be controlled extremely uniformly, AI 203 I
The film thickness and film quality of I can be made extremely uniform over the entire film.

After completing the main steps of the method of the present invention as described above, the AI
A polycrystalline silicon film having a thickness of 400× is deposited on the 203 film 4, and a resist pattern is further formed on the polycrystalline silicon film. Using this resist pattern as a mask, the polycrystalline silicon film is selectively etched, and at the same time the A1□03 film 4 is selectively etched, thereby forming a gate made of polycrystalline silicon as shown in FIG. 1(e''). Electrode 5 and A1 of the same shape located directly below it
□0ilit4a is formed. Then the gate electrode 5
After ion-implanting an N-type impurity into the semiconductor substrate 1 through the surrounding gate oxide film 3 using as a mask, heat treatment is performed to form an N-type impurity across the gate electrode 5 as shown in FIG. A source region 1B and a drain region 1C of the concentration layer are formed. Furthermore, Fig. 1(f)
As shown in FIG. ! After forming 116, a source electrode 7 and a drain electrode 8 are formed to form the M of the N-channel enhancement type double insulating film structure.
The main part of the OS semiconductor device is completed.

FIG. 2 shows the distribution of the in-wafer threshold voltage V th of the MAO8 structure semiconductor device manufactured by the method of the present invention and the in-wafer threshold voltage V th of the MAO3 structure semiconductor device manufactured by the conventional method. This is a graph comparing and displaying the distribution. In the second factor, the horizontal axis is the radial distance R(ell) from the center of the wafer, the vertical axis is the threshold voltage (A-B・U) of the elements in the wafer, and the solid curve A , and the circled points indicate the V of the semiconductor device manufactured by the method of the present invention.
The value of th, the dotted curve B, and the point marked with an X are the values of V bh of the semiconductor device manufactured by the conventional method.

From the results shown in FIG. 2, it can be seen that semiconductor devices manufactured using the conventional method have a variation of ±12% within the same wafer, but when manufactured using the method of the present invention, each element within the same wafer varies. The variation in V+,h was found to be ±5%. That is, it can be seen that according to the method of the present invention, substantially uniform elements can be obtained within the same wafer.

FIG. 3 shows the results of a blowing test (pass rate) for a semiconductor device with an MAO8 structure manufactured by the method of the present invention and the results (pass rate) of a semiconductor device with an MAO8 structure manufactured by a conventional method. In FIG. 3, which is a graph showing a comparative display over a period of The x mark and the dotted curve B are the values of the element manufactured by the conventional method.

As is clear from FIG. 3, devices manufactured by the method of the present invention always have a higher pass rate than devices manufactured by the conventional method. Therefore, the method of the present invention has an average yield of 1% higher than the conventional method. It was found that this could be improved.

Note that Ti, 7a1W, and Zl' are used instead of A1.

It has become clear that the same results can be obtained using metals such as Hf and Pb.

[Effects of the Invention] As explained above, according to the method of the present invention, it is possible to equalize the performance of devices within one wafer and to significantly improve the device yield. High performance double insulating film type MOS without significant yield deterioration even as the diameter increases and device integration progresses.
Semiconductor devices can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a device for explaining one embodiment of the process of the method of the present invention, and FIG. 2 is a distribution of the threshold Ifi W pressure V th within the wafer of semiconductor devices manufactured by the method of the present invention within the same wafer. A graph comparing and showing the distribution of threshold voltage within the same wafer of semiconductor devices manufactured by the conventional method and the distribution of the threshold voltage within the same wafer, and FIG. 3 shows the passing rate of the blowing test of the semiconductor device manufactured by the method of the present invention and the conventional method 3 is a graph comparing and displaying the pass rate of semiconductor devices manufactured in 2008 over a predetermined period of time. 1... Semiconductor substrate, 2... Field oxide film, 3
...Gate oxide film, 4...A1□o3 film, 4a
...AI 203 layer, 5...gate electrode, 6.
...Gate protective film, 7...Source electrode, 8...
Drain electrode, 1A...channel cut region, 1
B...source region, 1C...drain region. Patent applicant: Toshiba Corporation Figure 1

Claims (1)

[Claims] 1. After ion-implanting at least one metal atom among Al, Ti, Ta, W, Zr, Hf, and Pb and oxygen atoms into an oxide film formed on a 1-conductivity type or 2-conductivity type semiconductor substrate, heat treatment is performed. A method of manufacturing a MOS semiconductor device, comprising forming an oxide layer of the metal atoms on the upper layer of the oxide film, and further forming a gate electrode on the oxide layer.