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JPS62145821A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS62145821A
JPS62145821A JP28833285A JP28833285A JPS62145821A JP S62145821 A JPS62145821 A JP S62145821A JP 28833285 A JP28833285 A JP 28833285A JP 28833285 A JP28833285 A JP 28833285A JP S62145821 A JPS62145821 A JP S62145821A
Authority
JP
Japan
Prior art keywords
film
oxidation
substrate
oxide film
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28833285A
Other languages
Japanese (ja)
Inventor
Yasuhide Kamata
鎌田 康秀
Norio Koide
小出 典男
Toshiyuki Yamazaki
山崎 利幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP28833285A priority Critical patent/JPS62145821A/en
Publication of JPS62145821A publication Critical patent/JPS62145821A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To perform an oxidation required for two steps in a conventional method in a single step by concurrently forming oxide films of different thickness in the same step. CONSTITUTION:A buffer oxide film 2 is formed by a thermal oxidation on a substrate 1, covered with a photoresist film 3, exposed, and photosensed to allow the photoresist film 3 of desired pattern to remain. After the semiconductor substrate 1 is exposed, the substrate 1 is thermally oxidized at low temperature to concurrently form oxide films 5 of different thicknesses. That, is, the film 3 is removed by plasma etching, the film 2 is then removed by plasma etching, the surface of the substrate 1 is exposed, and a reoxidized film 5 is adhered by thermal oxidation on the substrate 1 after the substrate 1 is exposed. In this thermal oxidation, the oxidation is accelerated by treating at low temperature, and performs a pyrooxidation (a hydrogen combustion oxidizing method) at 875 deg.C for 20min.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は酸化珪素膜の形成方法、特に短時間に厚く酸化
珪素膜を形成する方法に関し、更に同時に異なる厚みの
酸化珪素膜を形成する方法に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for forming a silicon oxide film, particularly a method for forming a thick silicon oxide film in a short time, and further relates to a method for simultaneously forming silicon oxide films of different thicknesses. Regarding the method.

(ロ)従来の技術 半導体装置の製造に際し、シリコン酸化膜は重要な役割
を果す。素子の表面保護膜、選択拡散用被膜、配線間の
絶縁膜等として用いられることは周知である。このシリ
コン酸化膜は種々の形成方法があり、熱酸化法の他にプ
ラズマ酸化法、陽極酸化法等が知られている。しかし熱
酸化法が最も実用的な方法であり、現在の半導体装置の
製造に際しては熱酸化法を多用している。
(b) Conventional Technology Silicon oxide films play an important role in the manufacture of semiconductor devices. It is well known that it is used as a surface protection film for elements, a film for selective diffusion, an insulating film between wirings, and the like. There are various methods for forming this silicon oxide film, including thermal oxidation, plasma oxidation, anodic oxidation, and the like. However, the thermal oxidation method is the most practical method, and is often used in the manufacture of current semiconductor devices.

熱酸化法にはドライO6酸化法、ウェット0.酸化法、
スチーム酸化法、水素燃焼酸化法等がある。ドライO8
酸化法は拡散炉内に0.ガスとN。
Thermal oxidation methods include dry O6 oxidation method and wet O6 oxidation method. oxidation method,
There are steam oxidation methods, hydrogen combustion oxidation methods, etc. dry O8
The oxidation method uses 0.0% in the diffusion furnace. Gas and N.

ガスとを導入してウェハ表面にシリコン酸化膜を形成す
るものである。ウェットO3酸化法は拡散炉内に水中を
通したO、ガスを導入してシリコン酸化膜を形成するも
のである。スチーム酸化法は拡散炉内に水蒸気を導入し
てウェハ表面にシリコン酸化膜を形成するものである。
A silicon oxide film is formed on the wafer surface by introducing a gas. The wet O3 oxidation method forms a silicon oxide film by introducing O gas passed through water into a diffusion furnace. The steam oxidation method involves introducing water vapor into a diffusion furnace to form a silicon oxide film on the wafer surface.

陽極酸化法はRFスパッタリング装置を用いて陽極側電
極にシリコン板を配置し、酸素ガスの存在のもとに60
0〜1000℃の高温に加熱し、シリコン板表面にプラ
ズマ中で分解したOトを反応させてシリコン酸化膜を形
成するものである。
In the anodic oxidation method, a silicon plate is placed on the anode side electrode using an RF sputtering device, and a silicon plate is placed on the anode side electrode.
The silicon plate is heated to a high temperature of 0 to 1000° C., and the surface of the silicon plate is reacted with oxygen decomposed in plasma to form a silicon oxide film.

斯る熱酸化法ではシリコンウェハをドライO8の雰囲気
中で約1200°Cの加熱処理を行うと60分間で20
00人のシリコン酸化膜を形成できる。また10000
人のシリコン酸化膜を形成するには約4時間の1000
℃のスチーム酸化を必要とする。
In such a thermal oxidation method, when a silicon wafer is heated at approximately 1200°C in a dry O8 atmosphere, 20
000 silicon oxide films can be formed. 10000 again
It takes about 4 hours to form a human silicon oxide film.
°C requires steam oxidation.

(ハ)発明が解決しようとする問題点 しかしながら斯上した熱酸化法では最新LSIプロセス
技術、工業調査会、1983年5月発行の第131頁の
図2.2.4等に示される様に1/2重則で決められる
酸化時間だけ熱酸化をする必要がある。このため特に厚
いシリコン酸化膜を熱酸化法で形成する場合は長時間の
加熱処理を必要とする欠点を有していた。また基板上に
同時に異なる厚みのシリコン酸化膜を熱酸化法で形成す
ることができない欠点も有していた。
(c) Problems to be solved by the invention However, in the thermal oxidation method mentioned above, as shown in Figure 2.2.4 etc. on page 131 of Latest LSI Process Technology, Industrial Research Association, May 1983 issue. It is necessary to perform thermal oxidation for the oxidation time determined by the 1/2 double rule. For this reason, when a particularly thick silicon oxide film is formed by thermal oxidation, it has the disadvantage of requiring a long heat treatment. Another drawback is that silicon oxide films of different thicknesses cannot be simultaneously formed on a substrate by thermal oxidation.

(ニ)問題点を解決するための手段 本発明は斯る欠点に鑑みてなされ、半導体基板(1)の
−主面にイオン濃度のピークがその表面あるいは近傍に
位置する様な不純物のイオン注入層(4)を選択的に形
成する工程と半導体基板(1)表面を露出した後低温で
熱酸化して異なる厚みの酸化膜(5)を同時に形成する
工程とにより従来の欠点を改善した半導体装置の製造方
法を提供するものである。
(d) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and involves ion implantation of impurities such that the peak of ion concentration is located on or near the main surface of the semiconductor substrate (1). A semiconductor that improves the drawbacks of conventional semiconductors through the process of selectively forming the layer (4) and the process of exposing the surface of the semiconductor substrate (1) and then thermally oxidizing it at low temperatures to simultaneously form oxide films (5) of different thicknesses. A method for manufacturing the device is provided.

(*)作用 本発明に依れば、イオン注入に於けるイオン濃度のピー
ク位置での基板表面の結晶構造の変化、欠陥、転位等を
利用して低温増速酸化を行い、短時間で厚いシリコン酸
化膜(5)を実現している。
(*) Function According to the present invention, low-temperature accelerated oxidation is performed by utilizing changes in the crystal structure, defects, dislocations, etc. of the substrate surface at the peak position of ion concentration during ion implantation, and a thick layer can be formed in a short time. A silicon oxide film (5) is realized.

この結果イオン注入層(4)を基板(1)表面に選択的
に設けることにより同一の酸化工程で異なる厚みの酸化
膜(5)を形成できる。
As a result, by selectively providing the ion implantation layer (4) on the surface of the substrate (1), oxide films (5) of different thicknesses can be formed in the same oxidation process.

(へ)実施例 本発明の実施例を第1図乃至第7図を参照して詳述する
(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7.

本発明の第1の工程は半導体基板(1)の−主面にイオ
ン濃度のピークがその表面あるいは近傍に位置する様な
不純物のイオン注入層(4)を選択的に形成することに
ある(第1図イ乃至第1図ハ)。
The first step of the present invention is to selectively form an ion-implanted impurity layer (4) on the main surface of the semiconductor substrate (1) such that the peak of ion concentration is located at or near the surface ( Figures 1A to 1C).

本工程では第1図イに示す如く、半導体基板(1)とし
てP型シリコンで、10〜14Ω国のものを用い、基板
(1)表面にバッファ酸化膜(2)を熱酸化により形成
する。バッファ酸化膜(2)の厚みは第3図に示す特性
図より決められ、不純物のイオン濃度のピークが基板表
面に来る様にその厚みを決定している。具体的にはヒ素
(A、)をイオン注入する場合、加速電圧40Keyで
は220人の厚みに、加速電圧80KeVでは380人
の厚みに、加速電圧130 KeVでは620人の厚み
に設定する。バッファ酸化膜(2)の代りにポリシリコ
ン膜、シリコン窒化膜を用いても良い。
In this step, as shown in FIG. 1A, a P-type silicon of 10 to 14 Ω is used as the semiconductor substrate (1), and a buffer oxide film (2) is formed on the surface of the substrate (1) by thermal oxidation. The thickness of the buffer oxide film (2) is determined based on the characteristic diagram shown in FIG. 3, and is determined so that the peak of the impurity ion concentration is located on the substrate surface. Specifically, when arsenic (A) is ion-implanted, the thickness is set to 220 people at an acceleration voltage of 40 Key, the thickness is set to 380 people at an acceleration voltage of 80 KeV, and the thickness is set to 620 people at an acceleration voltage of 130 KeV. A polysilicon film or a silicon nitride film may be used instead of the buffer oxide film (2).

続いて本工程では第1図口に示す如く、バッファ酸化膜
(2)上にホトレジスト膜(3)を塗布し、露光感光し
て所望のパターンのホトレジスト膜(3)を残存させる
。ホトレジスト膜(3)はイオン注入のマスクとして働
く。
Subsequently, in this step, as shown in the opening of FIG. 1, a photoresist film (3) is coated on the buffer oxide film (2) and exposed to light to leave a desired pattern of the photoresist film (3). The photoresist film (3) acts as a mask for ion implantation.

更に本工程では第1図ハに示す如く、バッファ酸化膜(
2)およびホトレジスト膜(3)上から不純物のイオン
注入を行い、イオン注入層(4)を選択的に形成してい
る。このイオン注入では不純物の種=4− 類(A、、P、B等)、ドーズ量、加速電圧を所定の値
に選択し、イオン注入層(4)のイオン濃度のピーク位
置が基板(1)の表面あるいはその近傍に来る様にする
。イオン注入に依るイオン濃度は第2図・に示す如く、
イオンの平均飛程R,がバッファ酸化膜(2)の厚みと
略等しくなる様に設定すると実線で示すガウス分布をす
る。またイオン注入のドーズ量は第6図に示す特性図よ
り増速酸化の効果がある通常の2倍以上の範囲内で選ば
れ、ヒ素の場合は加速電圧80KeVで6×10°ef
ll−”以上に、リンの場合は加速電圧80KeVでI
 X 10 ”cm−’以上に設定される。本実施例で
はヒ素を不純物として用い、ドーズ量5XIQ”cm−
1に設定している。
Furthermore, in this step, as shown in Figure 1C, a buffer oxide film (
2) and impurity ions are implanted from above the photoresist film (3) to selectively form an ion implantation layer (4). In this ion implantation, impurity species = 4-class (A, P, B, etc.), dose amount, and acceleration voltage are selected to predetermined values, and the peak position of the ion concentration in the ion implantation layer (4) is set to the substrate (1). ) on or near the surface. The ion concentration due to ion implantation is as shown in Figure 2.
When the average range R of the ions is set to be approximately equal to the thickness of the buffer oxide film (2), a Gaussian distribution is obtained as shown by the solid line. In addition, the dose of ion implantation is selected within the range of more than twice the normal dose to achieve the effect of accelerated oxidation, as shown in the characteristic diagram shown in Figure 6. In the case of arsenic, the dose is 6
In the case of phosphorus, I
X 10 "cm-' or more. In this example, arsenic is used as an impurity, and the dose is 5XIQ"cm-'.
It is set to 1.

本発明の第2の工程は半導体基板(1)表面を露出した
後、低温で基板(1)を熱酸化して異なる厚みの酸化膜
(5)を同時に形成することにある(第1図二)。
The second step of the present invention consists in exposing the surface of the semiconductor substrate (1) and then thermally oxidizing the substrate (1) at a low temperature to simultaneously form oxide films (5) of different thicknesses (Fig. 1, 2). ).

本工程は本発明の最も特徴とする工程であり、ホトレジ
スト膜(3)をプラズマエッチ等で除去した後バッファ
酸化膜(2)をプラズマエッチ等のドライエツチングあ
るいはHF等によるウェットエツチングにより除去し、
基板(1)表面を露出する。基板(1)表面の露出後、
基板け)表面に熱酸化により再酸化膜(5)を付着する
。この熱酸化処理に於いて低温で処理することにより増
速酸化を行っており、実施例では875℃で20分間の
パイロ酸化(水素燃焼酸化法)を行っている。低温処理
する理由を第5図を参照して説明すると、ヒ素の活性化
率を低く抑えて熱酸化しないと増速酸化の効果が得られ
ないためである。ヒ素を加速電圧100 KeVでドー
ズ量5X10”an−”でイオン注入した場合、活性化
率を50%以下に抑えるには950°C以下で熱処理を
しなくてはならない。従来ではイオン注入で形成される
基板表面の欠陥の回復のため1000°C以上で30分
間のアニールを必ず行っているのに対して、本発明では
低温で処理して欠陥をそのまま利用して増速酸化する点
に特徴がある。
This step is the most characteristic step of the present invention, in which the photoresist film (3) is removed by plasma etching or the like, and then the buffer oxide film (2) is removed by dry etching such as plasma etching or wet etching using HF or the like.
Expose the surface of the substrate (1). After exposing the surface of the substrate (1),
A re-oxidized film (5) is attached to the surface of the substrate by thermal oxidation. In this thermal oxidation treatment, accelerated oxidation is performed by processing at a low temperature, and in the example, pyro oxidation (hydrogen combustion oxidation method) is performed at 875° C. for 20 minutes. The reason for performing the low-temperature treatment will be explained with reference to FIG. 5. This is because the effect of accelerated oxidation cannot be obtained unless the activation rate of arsenic is kept low and thermal oxidation is not performed. When arsenic is ion-implanted at an acceleration voltage of 100 KeV and a dose of 5×10 "an-", heat treatment must be performed at a temperature of 950° C. or less in order to suppress the activation rate to 50% or less. Conventionally, in order to recover defects on the substrate surface formed by ion implantation, annealing is always performed at 1000°C or higher for 30 minutes, but in the present invention, the process is performed at a low temperature and the defects are used as they are for growth. It is characterized by rapid oxidation.

本工程に於げる増速酸化の再酸化膜(5〉の厚みとバッ
ファ酸化膜(2)の厚みの関係を第4図を参照して説明
する。第4図はヒ素をドーズ量5X10”cm−”で加
速電圧40KeV、80KeV、  130Ke■の場
合の特性図であり、点線は1000”Cで30分間のア
ニールを行った基板の再酸化の特性図である。加速電圧
40KeVの場合、バッファ酸化膜(2)が約140人
のとき再酸化膜(5)の厚さは4000人とピークとな
る。加速電圧80KeVの場合、バッファ酸化膜(2)
が約350人のとき再酸化膜(5)の厚さは4000人
とピークとなる。更に加速電圧130KeVの場合、バ
ッファ酸化膜(2)が約600人のとき再酸化膜(5)
の厚さは4000人とピークとなる。この結果より再酸
化膜(5)がピークの厚みとなるのは第3図に示した如
く、イオン濃度のピークが基板(1)表面に位置する様
にバッファ酸化膜(2)の厚みを加速電圧40KeVで
220人、加速電圧80KeVで380人、加速電圧1
30KeVで620人とした値と良く一致していること
が明らかである。これから本発明の増速酸化は次の様に
解析される。イオン注入時の平均飛程R,近傍にイオン
注入による欠陥のピークが存在し、バッファ酸化膜(2
)の厚みをπ2の近傍に設定すると基板(1)表面に欠
陥ピークが現れる。
The relationship between the thickness of the re-oxidation film (5) in accelerated oxidation and the thickness of the buffer oxide film (2) in this process will be explained with reference to Figure 4. Figure 4 shows arsenic at a dose of 5X10''. cm-'' and acceleration voltages of 40 KeV, 80 KeV, and 130 Ke. When the oxide film (2) is approximately 140 thick, the thickness of the re-oxidized film (5) reaches a peak of 4000 thick.When the acceleration voltage is 80 KeV, the buffer oxide film (2)
When the number of people is about 350, the thickness of the re-oxidized film (5) reaches a peak of 4000 people. Furthermore, in the case of an accelerating voltage of 130 KeV, when the buffer oxide film (2) is about 600 layers, the re-oxidation film (5)
Its thickness peaks at 4,000 people. From this result, the thickness of the buffer oxide film (2) is accelerated so that the peak of ion concentration is located on the surface of the substrate (1), as shown in Figure 3. 220 people at voltage 40KeV, 380 people at acceleration voltage 80KeV, acceleration voltage 1
It is clear that this value agrees well with the value of 620 people at 30 KeV. The accelerated oxidation of the present invention will now be analyzed as follows. There is a peak of defects caused by ion implantation near the average range R during ion implantation, and the buffer oxide film (2
) is set near π2, a defect peak appears on the surface of the substrate (1).

この基板(1)表面を低温で熱酸化すると欠陥がアニー
ルされる前に酸化が進み、欠陥ピークによる増速酸化が
続くのである。
When the surface of this substrate (1) is thermally oxidized at a low temperature, oxidation proceeds before defects are annealed, and accelerated oxidation continues due to defect peaks.

第4図に示す点線の特性図はヒ素を加速電圧80 Ke
V、ドーズ量5×10 ”Cm−”でイオン注入した後
、1000℃で30分間アニール処理をした場合であり
、再酸化膜(5)は875°Cで30分間のパイロ酸化
しても増速酸化されず約1700人の厚みにしかならな
い。またバッファ酸化膜厚に対して点線の特性はピーク
を形成せず、アニールにより基板表面の欠陥が回復して
いることが分る。
The dotted line characteristic diagram shown in Figure 4 shows arsenic at an accelerating voltage of 80 Ke.
This is the case where ions were implanted at a dose of 5 x 10 "Cm-" and then annealed at 1000°C for 30 minutes. It is not oxidized quickly and becomes only about 1,700 people thick. Furthermore, the characteristics indicated by the dotted line do not form a peak with respect to the buffer oxide film thickness, indicating that defects on the substrate surface are recovered by annealing.

この実験より本発明の増速酸化は基板表面の欠陥ピーク
に依ることが明らかである。
From this experiment, it is clear that the accelerated oxidation of the present invention depends on defect peaks on the substrate surface.

第7図に原子量に対する再酸化膜(5)の増速度の特性
を示す。このグラフは酸化条件を20分間のドライ02
酸化、20分間のパイロ酸化とし、基板へのイオン注入
を加速室JEf 80 Key、ドーズ量5×10I6
cITl−1で行い、/< y −77酸化膜(2) 
ハ加速電圧80KeVで増速度がピークとなる膜厚に設
定している。増速度はバージンウェハの同一酸化条件の
ときの膜厚を基準としている。第7図から明らかな様に
不純物としてボロン(B)を用いたときは増速度1.3
倍となり、リン(P)を用いたときは増速度3.5倍と
なり、ヒ素(A、)を用いたときは増速度9倍となる。
FIG. 7 shows the speed increase characteristics of the reoxidized film (5) with respect to its atomic weight. This graph shows the oxidation conditions: 20 minutes dry 02
Oxidation, pyrooxidation for 20 minutes, and ion implantation into the substrate in an acceleration chamber JEf 80 Key, dose 5×10I6
Performed with cITl-1, /< y -77 oxide film (2)
The film thickness is set so that the acceleration peaks at an acceleration voltage of 80 KeV. The speed increase is based on the film thickness of a virgin wafer under the same oxidation conditions. As is clear from Figure 7, when boron (B) is used as an impurity, the speed increase is 1.3.
When phosphorus (P) is used, the speed is increased 3.5 times, and when arsenic (A, ) is used, the speed is increased 9 times.

これから原子量が大きい程欠陥が大きくなり、増速酸化
が促進されることが分る。
It can be seen from this that the larger the atomic weight, the larger the defects, and the more accelerated oxidation is promoted.

従って本工程ではイオン注入層(4)上には増速酸化さ
れて厚い再酸化膜(6)が形成され、他の基板(1)表
面には通常の酸化により薄い再酸化膜(7)が形成され
る。具体的にはヒ素を加速電圧80KeVでドーズ量5
 X 10 ”cm−”でイオン注入したとき、厚い再
酸化膜(6)を約7000人の浮きに付着すると薄い再
酸化膜(7)は約100人同時に付着できる。これから
厚い再酸化膜(6)をフィールド酸化膜とし、薄い再酸
化膜(7)をゲート酸化膜として利用できる。
Therefore, in this step, a thick re-oxidized film (6) is formed on the ion-implanted layer (4) through accelerated oxidation, and a thin re-oxidized film (7) is formed on the surface of the other substrate (1) through normal oxidation. It is formed. Specifically, arsenic was applied at a dose of 5 at an acceleration voltage of 80 KeV.
When ion implantation is carried out at X 10 "cm-", if a thick re-oxidized film (6) is attached to floats of about 7000 people, a thin re-oxidized film (7) can be attached to about 100 people at the same time. From now on, the thick reoxidation film (6) can be used as a field oxide film, and the thin reoxidation film (7) can be used as a gate oxide film.

(ト)発明の効果 本発明に依ればシリコン酸化膜を増速酸化により短時間
で厚く付着できるので極めて作業効率の向上が図れる利
点を有する。具体的には本発明では875℃で20分間
のパイロ酸化で約4000人の再酸化膜(5)を形成で
きるのに対し従来では1000℃で1.5時間のウェッ
トO2酸化で約4000人の酸化膜を形成できる。
(g) Effects of the Invention According to the present invention, a silicon oxide film can be thickly deposited in a short time by accelerated oxidation, so that the work efficiency can be greatly improved. Specifically, in the present invention, a reoxidation film (5) of about 4000 people can be formed by pyrooxidation at 875°C for 20 minutes, whereas in the conventional method, about 4000 people can be formed by wet O2 oxidation at 1000°C for 1.5 hours. An oxide film can be formed.

また本発明では同一工程で異なる厚みの酸化膜(5)を
同時に形成できるので、従来2工程を要した酸化処理を
単一工程で実現できる利点を有する。しかも本発明では
薄い再酸化膜(7)の酸化時間で厚い再酸化膜(6)を
形成でき極めて効率が良くなる。
Furthermore, in the present invention, since oxide films (5) of different thicknesses can be formed simultaneously in the same process, there is an advantage that the oxidation treatment, which conventionally required two processes, can be realized in a single process. Moreover, in the present invention, a thick reoxidized film (6) can be formed in the oxidation time of a thin reoxidized film (7), resulting in extremely high efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図イ乃至第1図工は本発明の半導体装置の製造方法
を説明する断面図、第2図は本発明に於けるイオン濃度
のピークを説明する断面図、第3図は本発明に於けるバ
ッファ酸化膜厚とイオン濃度の関係を説明する特性図、
第4図は本発明に於けるバッファ酸化膜厚と再酸化膜厚
の関係を説明する特性図、第5図は本発明に於けるアニ
ール温度とヒ素の活性化率の関係を説明する特性図、第
6図は本発明に於けるドーズ量と再酸化膜厚の関係を説
明する特性図、第7図は本発明に於ける原子量と再酸化
膜の増速度の関係を説明する特性図である。 (1)は半導体基板、(2)はバッファ酸化膜、(3)
はホトレジスト膜、(4)はイオン注入層、(5)は再
酸化膜である。 出願人  三洋電機株式会社 外1名 代理人  弁理士  佐 野 静 夫 第1図イ 第1図口 第1図ハ 第1図工
1A to 1D are cross-sectional views for explaining the method of manufacturing a semiconductor device of the present invention, FIG. 2 is a cross-sectional view for explaining the peak of ion concentration in the present invention, and FIG. A characteristic diagram explaining the relationship between buffer oxide film thickness and ion concentration,
FIG. 4 is a characteristic diagram illustrating the relationship between buffer oxide film thickness and re-oxidation film thickness in the present invention, and FIG. 5 is a characteristic diagram illustrating the relationship between annealing temperature and arsenic activation rate in the present invention. , FIG. 6 is a characteristic diagram illustrating the relationship between dose amount and re-oxidation film thickness in the present invention, and FIG. 7 is a characteristic diagram illustrating the relationship between atomic weight and re-oxidation film speed increase in the present invention. be. (1) is a semiconductor substrate, (2) is a buffer oxide film, (3)
is a photoresist film, (4) is an ion implantation layer, and (5) is a reoxidation film. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano Figure 1 A Figure 1 mouth Figure 1 C Figure 1 Design

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板の一主面にイオン濃度のピークがその表
面あるいは近傍に位置する様な不純物のイオン注入層を
選択的に形成する工程と前記半導体基板表面を露出した
後低温で基板を熱酸化して異なる厚みの酸化膜を同時に
形成する工程とを有することを特徴とする半導体装置の
製造方法。
1. A step of selectively forming an ion-implanted impurity layer on one main surface of the semiconductor substrate such that the peak of ion concentration is located at or near the surface, and after exposing the surface of the semiconductor substrate, the substrate is thermally oxidized at a low temperature. 1. A method of manufacturing a semiconductor device, comprising the step of simultaneously forming oxide films of different thicknesses.
JP28833285A 1985-12-20 1985-12-20 Manufacture of semiconductor device Pending JPS62145821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28833285A JPS62145821A (en) 1985-12-20 1985-12-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28833285A JPS62145821A (en) 1985-12-20 1985-12-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62145821A true JPS62145821A (en) 1987-06-29

Family

ID=17728816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28833285A Pending JPS62145821A (en) 1985-12-20 1985-12-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62145821A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0291960A (en) * 1988-09-29 1990-03-30 Rohm Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0291960A (en) * 1988-09-29 1990-03-30 Rohm Co Ltd Manufacture of semiconductor device

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