JPH09107101A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: Amorphous semiconductor manufacturing method
The purpose is to reduce the resistance of the silicide layer formed on the Si film and to stabilize the resistance value. SOLUTION: A step of forming an amorphous Si film 4 on a substrate 1, a step of roughening the surface of the amorphous Si film 4, and a metal film 6 on the surface of the roughened amorphous Si film.
And the amorphous Si with the metal film 6 deposited thereon.
The film is formed by heat treatment in an inert gas atmosphere to form a silicide layer 7 on the surface of the amorphous Si film 4.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method for manufacturing a semiconductor device. Amorphous Si thin film transistors are widely used as driving elements for liquid crystal display panels because they can be easily integrated in a large area. However, since the amorphous Si film has high film resistance and the heat treatment is limited to a low temperature range, it is difficult to reduce the parasitic resistance and the parasitic capacitance, and this causes deterioration of the device performance, so improvement thereof is desired. .

[0002]

2. Description of the Related Art Amorphous Si thin-film transistors are manufactured by incorporating manufacturing technologies that have been used in the manufacture of single crystal silicon ICs to improve device performance and yield, such as ion implantation technology and silicide formation technology. There is. FIG. 4 and FIG. 5 show the main manufacturing steps of a conventional amorphous Si thin film transistor using these techniques. First, as shown in FIG. 4 (a), a metal film of Cr, Ti, or the like is deposited on an insulating substrate 1 made of glass or the like by a sputter deposition method, and this is patterned to form a gate electrode 2. . Then, a SiN film is deposited thereon by the plasma CVD method to form the gate insulating film 3, and subsequently an amorphous Si film 4 is formed by using the plasma CVD method.
Further, a SiN film is deposited on this and patterned to form a channel protection film 5. The amorphous Si film 4 immediately below the channel protective film 5 functions as a channel region.

Next, as shown in FIG. 4B, after patterning the amorphous Si film 4 to perform element isolation, ion implantation using As or P is performed using the channel protective film 5 as a mask. As a result, the amorphous Si film 4 other than the channel region is converted into n ⁺ type and becomes source / drain regions.

Then, as shown in FIG. 4 (c), a refractory metal film 6 such as Cr or Ti is deposited by the sputter deposition method. Then, when heat-treated in a nitrogen atmosphere, the metal element diffuses into the amorphous Si layer 4 excluding the channel region, and the layer near the surface is converted into a compound of metal and Si, that is, a silicide layer 7.

Next, as shown in FIG. 5D, the source / drain electrodes 8 are formed on the silicide layer 7 by patterning the metal film 6. As described above, since the source / drain electrode 8 is in contact with the amorphous Si film 4 via the silicide layer 7, the amorphous Si film 4
The contact resistance can be reduced as compared with the case where the source / drain electrodes 8 are directly formed on the upper surface.

Next, as shown in FIG. 5 (e), SiN is formed on the entire surface.
A contact hole 10 is formed after the film is deposited to form the interlayer insulating film 9. After that, an amorphous Si thin film transistor is completed by taking out the wiring electrode from the source / drain electrode 8 through the contact hole 10, but the description of these steps will be omitted.

[0007]

As described above,
By forming the silicide layer 7 on the surface of the amorphous Si film 4, the contact resistance between the amorphous Si film 4 and the source / drain electrodes 8 can be reduced. All of these processes apply the silicide formation technology used in the fabrication of single crystal silicon ICs to the fabrication of amorphous Si thin film transistors.

However, while the heat treatment temperature at the time of silicide formation can be set to about 1000 ° C. in the production of a single crystal silicon IC, the heat treatment temperature is limited to about 200 to 300 ° C. in the production of an amorphous Si thin film transistor. As a result, in the heat treatment for forming the silicide layer described with reference to FIG. 4 (c), the diffusion of the metal element into the amorphous Si film 4 becomes insufficient, and the resistance value of the silicide layer 7 cannot be lowered sufficiently. Therefore, there is a problem that the contact resistance is not sufficiently reduced.

As shown in FIG. 5D, when the source / drain electrode 8 is formed on the silicide layer 7, the surface of the silicide layer 7 between the channel protective film 5 and the source / drain electrode 8 is exposed to the atmosphere. Will be exposed to. An oxide layer is formed on the exposed surface of the silicide layer 7 by combining with oxygen in the atmosphere, but since the oxidation progresses in a low temperature region near room temperature, the oxide layer is extremely thin and oxygen in the atmosphere easily passes through. And diffuses into the silicide layer 7 to increase its resistance value. Since the oxidation process as described above gradually progresses according to the time when the surface of the silicide layer 7 is exposed, the resistance value of the silicide layer 7 is also manufactured when the time of exposure to the atmosphere is different in each manufacturing process. There is a problem that it varies depending on the process, which causes variations in contact resistance of the source / drain electrodes 8.

Therefore, an object of the present invention is to reduce the resistance of a silicide layer formed on an amorphous Si film and to stabilize its resistance value.

[0011]

[Means for Solving the Problems] To solve the above problems, a step of forming an amorphous Si film on a substrate, a step of roughening the surface of the amorphous Si film, and a roughened amorphous Si film A method of manufacturing a semiconductor device, comprising: a step of depositing a metal film; and a step of forming a silicide layer by heat-treating an amorphous Si film to which the metal film is deposited in an inert gas atmosphere, or the above semiconductor In the device manufacturing method, after the formation of the silicide layer, the amorphous Si
A method of manufacturing a semiconductor device, comprising: a step of removing at least a part of a metal film remaining on the film to expose a surface of the silicide layer; and a step of heat-treating the silicide layer in an oxygen atmosphere, or In the method for manufacturing a semiconductor device described above, prior to the heat treatment in an oxygen atmosphere,
This is achieved by a method for manufacturing a semiconductor device, which is characterized in that the silicide layer is covered with a heat resistant resin film.

As described above, when the surface of the amorphous Si film is roughened, its effective surface area increases, and the contact area with the metal film deposited on the amorphous Si film also increases. Since the diffusion of the metal element into the amorphous Si film is promoted, the content of the metal element in the silicide layer can be increased as compared with the case where the surface of the amorphous Si is not roughened. The resistance value can be reduced as compared with the conventional one.

As a method of roughening the surface of the amorphous Si film, there is, for example, anisotropic etching treatment. As is well known, amorphous Si is composed of an aggregate of fine crystal grains of about several tens to 100 Å, and various crystal planes of the fine crystal grains appear on the surface of the amorphous Si film. Therefore, when the surface of the amorphous Si is anisotropically etched, the size of each microcrystal grain changes at various rates depending on the etching rate of the crystal plane appearing on the surface of the microcrystal grain. As a result, fine irregularities are generated on the surface of the amorphous Si and the surface is roughened.

Further, in the present invention, the oxidation of the surface of the silicide layer is promoted by performing heat treatment in an oxygen atmosphere after forming the silicide. Since the formed oxide layer is thicker than in the case where the surface of the silicide layer is exposed to the atmosphere and is naturally oxidized, it functions as a barrier layer for preventing further diffusion of oxygen in the atmosphere into the silicide layer. . Therefore, the resistance value of the silicide layer after the heat treatment in the oxygen atmosphere is stabilized without further oxidation even when exposed to the air.

Further, when the surface of the silicide layer is directly heat-treated in an oxygen atmosphere as described above, the oxidation rate of the silicide layer may rapidly increase and the resistance value of the silicide layer may increase more than necessary. Therefore, if the surface of the silicide layer is covered with a heat-resistant resin film before the heat treatment in an oxygen atmosphere, the supply of oxygen to the silicide layer is reduced and the oxidation rate can be slowed down. Can be controlled more accurately.

[0016]

1 to 3 are sectional views showing main steps of an amorphous Si thin film transistor according to an embodiment of the present invention. First, as shown in FIG. 1A, a Cr film having a film thickness of 2000 Å is deposited on a substrate 1 by a sputter deposition method, and the Cr film is patterned to form a gate electrode 2. An insulating material such as glass is used as the substrate 1. Then, a SiN film having a film thickness of 3000 Å is deposited thereon to form a gate insulating film 3, and then an amorphous Si film 4 having a film thickness of 200 Å is formed by using a plasma CVD method. Further, a SiN film is deposited on this and patterned to form a channel protection film 5. The amorphous Si film 4 immediately below the channel protective film 5 functions as a channel region.

Next, as shown in FIG. 1 (b), the surface of the amorphous Si film 4 is etched for 30 seconds at room temperature with an alkaline etching solution, for example, a mixed solution of ethylenediamine / catechol / water. It is known that the alkaline etching solution can perform anisotropic etching treatment on Si, and the above treatment causes minute irregularities of about several tens to 100 Å on the surface of the amorphous Si film 4.

Next, as shown in FIG. 1 (c), the roughened amorphous Si film 4 is patterned to separate elements, and then As ions are implanted using the channel protective film 5 as a mask. As a result, amorphous Si excluding the channel region
The film 4 is converted into n ⁺ type and becomes a source / drain region.

Then, as shown in FIG. 2D, a metal film 6 having a film thickness of 3000 Å is deposited thereon by a sputter deposition method. As the metal film 6, a refractory metal such as Cr or Ti is usually used. Then, heat treatment temperature in a nitrogen gas atmosphere
Heat treatment is performed at 300 ° C for 30 minutes. As a result, the metal element diffuses into the amorphous Si film 4, and its surface is converted into the silicide layer 7. As a result of the above steps, the resistance value of the silicide layer 7 can be reduced as compared with the case where the surface of the amorphous Si film 4 is not roughened.

Next, as shown in FIG. 2E, the source / drain electrodes 8 are formed on the silicide layer 7 by patterning the metal film 6. Subsequently, when heat treatment is performed in an oxygen atmosphere at a heat treatment temperature of 250 ° C. for a heat treatment time of 30 minutes, the surface of the exposed silicide layer 7 between the channel protective film 5 and the source / drain electrode 8 is oxidized. The oxide layer formed on the surface of the silicide layer 7 has a function of preventing oxygen in the atmosphere from diffusing into the silicide layer 7.
The resistance value of is stabilized.

After that, steps similar to those described in the section of the prior art are used. That is, similar to the process shown in FIG. 2 (e), an SiN film is deposited on the entire surface to form an interlayer insulating film, contact holes are formed in this interlayer insulating film, and then a wiring pattern is taken out to form an amorphous Si thin film transistor Is completed.

In the process shown in FIG. 2 (e) in the above-mentioned embodiment, the source / drain electrodes 8 are formed on the silicide layer 7 and then heat treatment is carried out in an oxygen atmosphere. Since the exposed surface of the layer 7 is directly exposed to the oxygen atmosphere, the oxidation rate of the silicide layer 7 becomes faster, and as a result, the resistance value of the silicide layer 7 may become too large. Therefore, as shown in FIG. 2 (f), the resistance value of the silicide layer 7 can be easily controlled by slowing the oxidation rate by forming a heat resistant resin film 11 such as polyimide on the entire surface and then performing a heat treatment in an oxygen atmosphere. .
After this step, subsequently, as shown in FIG. 3 (g), a SiN film is deposited on the entire surface to form an interlayer insulating film 9, and the interlayer insulating film 9 and the heat resistant resin film 11 are patterned to form the contact holes 10.
And the wiring pattern is taken out to complete the amorphous Si thin film transistor.

[0023]

As described above, according to the present invention, the resistance of the silicide layer formed on the amorphous Si film is lowered and the resistance value thereof is stabilized, so that the characteristics of the amorphous Si thin film transistor can be improved. Be beneficial.

[Brief description of the drawings]

FIG. 1 is a process sectional view (1) according to an embodiment of the present invention.

FIG. 2 is a process sectional view according to an example of the present invention (No. 2)

FIG. 3 is a process sectional view according to an example of the present invention (part 3)

FIG. 4 is a process sectional view according to a conventional example (No. 1)

FIG. 5 is a process sectional view according to a conventional example (No. 2)

[Explanation of symbols]

1 substrate 7 silicide layer 2 gate electrode 8 source / drain electrode 3 gate insulating film 9 interlayer insulating film 4 amorphous Si film 10 contact hole 5 channel protective film 11 heat resistant resin film 6 metal film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/324

Claims (3)

[Claims] 1. A step of forming an amorphous Si film on a substrate, a step of roughening the surface of the amorphous Si film, and a step of depositing a metal film on the roughened amorphous Si film. A method of manufacturing a semiconductor device, comprising a step of forming a silicide layer by heat-treating an amorphous Si film on which a metal film is deposited in an inert gas atmosphere. 2. The amorphous Si after forming a silicide layer
2. The semiconductor device according to claim 1, further comprising a step of removing at least a part of the metal film remaining on the film to expose the surface of the silicide layer, and a step of heat-treating the silicide layer in an oxygen atmosphere. Manufacturing method. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the surface of the exposed silicide layer is covered with a heat resistant resin film before the heat treatment in an oxygen atmosphere.