JPS62291146A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62291146A JPS62291146A JP13661986A JP13661986A JPS62291146A JP S62291146 A JPS62291146 A JP S62291146A JP 13661986 A JP13661986 A JP 13661986A JP 13661986 A JP13661986 A JP 13661986A JP S62291146 A JPS62291146 A JP S62291146A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- hole
- oxide film
- silicon oxide
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 31
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000007516 Chrysanthemum Nutrition 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にアルミニウ
ム配線の形成方法に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming aluminum wiring.
従来、開孔部を有する絶縁膜上にアルミニウム配線を形
成する方法は、例えば、第2図(a) 、 (b)に示
すような方法で行なっている。すなわち、まず第2図(
a)に示すように、シリコン基板11に不純物拡散層1
2を形成し、シリコン基板表面をシリコン酸化膜13で
覆い、シリコン酸化膜13の所定の位置に開孔部14を
設ける。次に第2図(blのように、開孔部14を含む
シリコン酸化腺13上にアルミニウム9をスパッタ法に
て堆積し、写真食刻技術によりアルミニウム9を選択的
に食刻し、アルミ配m全形成する。Conventionally, aluminum wiring has been formed on an insulating film having openings by, for example, the method shown in FIGS. 2(a) and 2(b). In other words, first of all, Figure 2 (
As shown in a), an impurity diffusion layer 1 is formed on a silicon substrate 11.
2 is formed, the surface of the silicon substrate is covered with a silicon oxide film 13, and openings 14 are provided at predetermined positions of the silicon oxide film 13. Next, as shown in FIG. 2 (bl), aluminum 9 is deposited by sputtering on the silicon oxide gland 13 including the opening 14, and the aluminum 9 is selectively etched by photolithography. m completely formed.
上述した従来のアルミニウム配線形成法では、シリコン
酸化膜13に設けた開孔部14で、第2図(blに示し
たようにアルミニウム15の膜厚が薄くなる。このこと
は開孔部14の微細化に伴ない−そう顕著になり、アル
ミニウム配線15の開孔部14での断Anひきおこしや
すくシ、信頼性上好ましくない。In the conventional aluminum wiring forming method described above, the thickness of the aluminum 15 becomes thinner at the opening 14 provided in the silicon oxide film 13, as shown in FIG. As miniaturization progresses, this becomes more noticeable, and disconnections at the openings 14 of the aluminum wiring 15 are likely to occur, which is unfavorable in terms of reliability.
本発明の半導体装置の製造方法は、絶縁膜で破われた半
導体基板の前記絶縁膜に孔を開け、との開孔部を含む前
記絶縁膜」二に、バリア金籾層をはさんだアルミニウム
配線を形成する工程において、前記アルミ被着稜に、こ
のアルミに対し、660°C以上で熱処理することを含
んでいる。The method for manufacturing a semiconductor device of the present invention includes: forming a hole in the insulating film of a semiconductor substrate torn by the insulating film; The step of forming the aluminum coating includes heat treating the aluminum at 660° C. or higher.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(al〜(dlは本発明をMO8型半導体装置に
適用した一実施例の工程順の断面図である。まず、第1
図(alに示すように、シリコン基板1の上に熱酸化に
よりシリコン酸化膜2を形成し、さらに多結晶シリコン
ゲート[極3を形成した彼に、ソース領域4aドレイン
領域4bを形成し、つぎに気相成長法によりシリコン酸
化膜5を形成し、シリコン酸化膜5に開孔6を開ける。FIG. 1 (al to (dl) are cross-sectional views in the order of steps of an embodiment in which the present invention is applied to an MO8 type semiconductor device.
As shown in FIG. A silicon oxide film 5 is formed by a vapor phase growth method, and an opening 6 is made in the silicon oxide film 5.
次に第1図tblに示すように、窒化チタン膜7をスパ
ッタ法にて05μm堆積し、次にアルミニウム8をスパ
ッタ法にて1μm堆積した。ここで空化チタン膜7は熱
処理工程においてアルミニウムのシリコン基板中への拡
散を防止するだめのバリアメタルとして堆積したもので
ある。堆積直後のアルミニウム8は、シリコン酸化膜の
開孔部6において平坦部よシ膜厚が薄くなる。仁のこと
は開孔部6が微細になるほど顕著になる。次にランプア
ニール法によりN。Next, as shown in FIG. 1tbl, a titanium nitride film 7 was deposited to a thickness of 05 μm by sputtering, and then aluminum 8 was deposited to a thickness of 1 μm by sputtering. Here, the empty titanium film 7 is deposited as a barrier metal to prevent aluminum from diffusing into the silicon substrate during the heat treatment process. Immediately after deposition, the thickness of the aluminum 8 becomes thinner in the opening 6 of the silicon oxide film than in the flat part. The finer the apertures 6, the more noticeable the nicks become. Next, N was applied using the lamp annealing method.
雰囲気にて700°Cの温度で5秒間の熱処理を行なっ
て第1図[C)の状態にする。アルミニウムの融点は6
60°Cなので、700°Cの温度では1表面張力によ
り微細開孔部内においてもアルミニウムがIJ 70−
し、開孔部6でのアルミニウム8の形Ml善される。こ
こで窒化チタンのシリコン及びアルミニウムの拡散に対
する耐バリア性は、通常700”Cでは長時間、例えば
30分の熱処理を行えばなくなってしまうが、充分注意
して窒化チタン7を形成すれば、700°Cでも短時間
、例えは、5秒間の熱処理であれば、耐バリア性はなく
ならない。A heat treatment is performed in an atmosphere at a temperature of 700° C. for 5 seconds to obtain the state shown in FIG. 1 [C]. The melting point of aluminum is 6
60°C, so at a temperature of 700°C, aluminum has an IJ 70-
However, the shape of the aluminum 8 in the opening 6 is improved. The barrier resistance of titanium nitride against diffusion of silicon and aluminum usually disappears if heat treatment is performed for a long time, for example, 30 minutes at 700"C, but if titanium nitride 7 is formed with sufficient care, Even at °C, if heat treatment is performed for a short time, for example, 5 seconds, the barrier resistance will not be lost.
次に第1図(d)に示したように、写真食刻技術により
アルミニウム8を選択的に食刻し、アルミニウム配線8
aを形成してMO8型トランジスタを作製した。Next, as shown in FIG. 1(d), the aluminum wiring 8 is selectively etched by photolithography.
A was formed to fabricate an MO8 type transistor.
本実施例ではアルミニウムのりフローを行なうためにラ
ンプアニール法を採用したが、窒化チタンよりも耐熱性
に優れたバリアメタルを使用すれば、通常の炉による熱
処理を行なっても良い。In this embodiment, a lamp annealing method was adopted to perform the aluminum glue flow, but if a barrier metal having higher heat resistance than titanium nitride is used, heat treatment using a normal furnace may be performed.
以上説明したように本発明によれば、660’C以上の
熱処理を施して絶縁膜の開孔部でのアルミニウムをリフ
ローして開孔内のアルミの形状全変改することによシ、
微細開孔部においてもアルミニウム配線の断線を防止で
き、半導体装置の信頼性を著しく向上させる効果がある
。As explained above, according to the present invention, by performing heat treatment at 660'C or more and reflowing the aluminum in the opening of the insulating film, the shape of the aluminum inside the opening is completely changed.
Breaking of the aluminum wiring can be prevented even in the minute openings, which has the effect of significantly improving the reliability of the semiconductor device.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順の断面図、第2図(a) 、 (blは従来
の半導体装置のアルミ配線形成方法を説明するための断
面図である。
1.11・・・シリコン基板、2・・・シリコン熱酸化
膜、3・・・多結晶シリコンゲート電極、4a、4b・
・ソース嗜ドレイン領域、5・・・シリコン酸化膜、6
・・・絶縁膜の開孔、7・・窒化チタン膜、8,9・・
・菊 /口FIGS. 1(a) to (d) are cross-sectional views in the order of steps for explaining an embodiment of the present invention, and FIGS. 1.11...Silicon substrate, 2...Silicon thermal oxide film, 3...Polycrystalline silicon gate electrode, 4a, 4b.
- Source/drain region, 5...Silicon oxide film, 6
...Opening in insulating film, 7...Titanium nitride film, 8,9...
・Chrysanthemum/mouth
Claims (1)
る工程と、前記開孔を含む絶縁膜上にバリア金属層とア
ルミ層を形成する工程と、前記アルミに対し660℃以
上の熱処理を施す工程とを含むことを特徴とする半導体
装置の製造方法。A step of forming a hole in the insulating film on a semiconductor substrate covered with an insulating film, a step of forming a barrier metal layer and an aluminum layer on the insulating film including the hole, and a heat treatment of the aluminum at 660° C. or higher. A method for manufacturing a semiconductor device, comprising the step of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13661986A JPS62291146A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13661986A JPS62291146A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62291146A true JPS62291146A (en) | 1987-12-17 |
Family
ID=15179536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13661986A Pending JPS62291146A (en) | 1986-06-11 | 1986-06-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62291146A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02168626A (en) * | 1988-09-13 | 1990-06-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPH04320024A (en) * | 1991-03-20 | 1992-11-10 | Samsung Electron Co Ltd | Manufacture of semiconductor device |
US5227325A (en) * | 1992-04-02 | 1993-07-13 | Micron Technology, Incl | Method of forming a capacitor |
-
1986
- 1986-06-11 JP JP13661986A patent/JPS62291146A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02168626A (en) * | 1988-09-13 | 1990-06-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JPH04320024A (en) * | 1991-03-20 | 1992-11-10 | Samsung Electron Co Ltd | Manufacture of semiconductor device |
US5227325A (en) * | 1992-04-02 | 1993-07-13 | Micron Technology, Incl | Method of forming a capacitor |
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