JP3105508B2 - Refractory metal silicide coating to protect multilayer polycide structures - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates generally to the formation of polycide, and more particularly to a coating layer for improving the oxidation resistance and chemical stability of a polycide structure.

2. Description of the Related Art As MOS integrated circuits become more and more complex, the improvement in circuit performance usually associated with the reduction in the size of individual circuit elements has not been fully realized recently.
The benefits associated with reduced size are limited by the RC time constant of the long interconnect lines required to interconnect the increasing number of circuit elements. To reduce the resistance component of long interconnect lines, integrated circuit manufacturers have proposed refractory metals, refractory metal silicides, and polycrystalline silicon instead of the polycrystalline silicon traditionally used for gate-level interconnects. / A high melting point metal silicide composite film (referred to as polycide). Such materials have an interconnect sheet resistance of 1-3 Ω / □, compared to 10 Ω / □ for polycrystalline silicon only.

Polycide has lower resistance than before,
It has the advantage that it can be processed at higher temperatures after deposition than before. Current technology requires three layers to interconnect
This may be necessary in forming a high quality inter-layer oxide which may function as an insulating layer between the various metallization layers, although it may exceed one or four layers. Typically, such oxide layers require the use of deposited glass that has been reflowed at a temperature of 800-900C. Conventionally used metals such as aluminum melt at this temperature. Polycide is a relatively stable material with a high melting point such that no phase change occurs during formation of the interlayer oxide.

In considering a process, a number of polycide films can be selected. In forming the refractory metal silicide, a refractory metal such as titanium, tungsten, molybdenum, or tantalum is used. All these metals have good thermal and chemical stability, but have somewhat different resistance properties. The most desirable refractory metal silicide from the viewpoint of circuit operation is titanium silicide (titanium silicide) having the lowest electric resistance. In fact, titanium silicide is one of the few metals with lower electrical resistance than the simple metal from which silicide is formed.

One disadvantage of titanium silicide is that it is not as resistant to oxidation as other silicides. Thus, if the surface of the titanium silicide is oxidized after formation, the contact resistance of the interconnect between the titanium silicide and different levels may be increased. This is a common problem in most processing systems. Of course, this problem can be solved by using silicides that are more resistant to oxidation and more chemically stable, but such silicides do not exhibit the same resistance properties as titanium silicide. Therefore, it is necessary to improve the oxidation resistance of the silicide layer so as to exceed the oxidation resistance of titanium silicide, and not to impair the conductive properties and chemical stability of the polycide surface at all. .

SUMMARY OF THE INVENTION The presently disclosed and claimed invention includes a method of forming a polycide structure having an oxidation resistant coating formed on a surface thereof. In this method, first, a polycrystalline silicon layer is formed on a semiconductor substrate. After this operation, a first refractory metal layer is formed on the polycrystalline silicon layer.
Next, a refractory metal silicide composite layer is formed on the first refractory metal layer. The refractory metal silicide composite layer has a sheet resistance at least equal to or higher than the sheet resistance of the silicide obtained from the first refractory metal layer, and has chemical stability and oxidation resistance of the first refractory metal layer. Better than silicide. Next, the refractory metal layer is reacted with polycrystalline silicon extending downward to form silicide.
At that time, only a part of the silicon in the polycrystalline silicon layer is consumed. Next, a polycide structure is defined by patterning and etching techniques.

According to another embodiment of the present invention, the first refractory metal layer is formed from titanium and the refractory composite is tantalum silicide (tantalum silicide). Thus, a tantalum silicide layer is deposited on the titanium silicide in the resulting structure. The tantalum silicide layer has much greater chemical stability and improved oxidation resistance as compared to titanium silicide. In yet another embodiment of the invention, a gate oxide layer is located below the polysilicon layer.

For a more complete understanding of the present invention and its advantages, reference is now made to the accompanying drawings.

Embodiment Referring to FIG. 1, one of manufacturing processes of a semiconductor structure is described.
A cross-sectional view of the steps is shown. In a conventional method of manufacturing a MOS integrated circuit, a thin wafer of a predetermined conductive type semiconductor material is used.
For example, reference numeral 10 in FIG. 1 is first masked with a thick oxide layer. For simplicity, it is assumed that substrate 10 is a P-type material. However, it must be recognized that materials of the opposite conductivity type can be used. Next, the oxide is removed in accordance with the pattern, and impurities that affect the conductivity are diffused, so that only a region where a “moat” is to be formed is exposed. Next, desired impurities are diffused into the substrate 10 at a temperature suitable for diffusion. After obtaining the desired penetration depth and concentration and regrowth of oxide on the moat, the wafer is removed from the diffusion environment. A surface insulating layer 12, called a field oxide of silicon, is obtained during the oxide growth and diffusion steps of the method to produce a layer of sufficient thickness. As a result, depositing a thin metallization layer reduces the electric field generated during normal operation of the device, and adversely affects the operation of portions of the semiconductor device other than the portion where the insulating layer is intentionally thinned. It does not extend.

After forming the field oxide layer 12, various conventional cleaning steps are performed by exposing the surface of the silicon at the moat locations, and then a thin gate oxide layer 14 is deposited over the moat. Grow to 100-1,000Å. This will be called the gate oxide layer of the MOS transistor. The moat exposes the "unreacted" portion of the silicon deeply to form a gate oxide layer 14 on its surface, to form a substantially intact gate oxide layer.

After the gate oxide layer 14 is formed, a polycrystalline silicon layer (poly layer) 16 is formed on the substrate to a thickness of about 2,000 to 4,
Deposit to 000Å. Next, an N-type impurity is diffused or implanted into the poly layer 16 to reduce the sheet resistance to about 10-20 Ω / □. Generally, phosphorus is used as the N-type dopant. By using the CVD method, the poly layer 16 actually becomes the same shape and matches the shape of the substrate 10. Here, the “same shape” means that the coating state of the film is conformal to the underlying step
It is used as a term that means

Reference is now made to FIG. After forming the poly layer 16, a vitrified portion is removed from the surface using diluted HF in a cleaning process, and a titanium layer 18 is deposited thereon. Titanium is a refractory metal and is converted to titanium silicide, as described below. Titanium silicide is widely used in the industry to reduce the sheet resistance of long poly layers. The poly layer 16 is necessary so that the underlying gate oxide is scarcely scratched. At present, there is no technique for depositing the refractory metal layer 18 directly on the gate oxide layer. Therefore, the poly layer 16 is used as a “buffer layer”. On the other hand, titanium silicide formed later from the titanium layer 18 has desired conductive properties.

Titanium layer 18 is deposited on the substrate by physical vapor deposition. As the physical vapor deposition method, either a sputtering method or a vapor deposition method can be used. In the preferred embodiment, titanium is sputtered using a Varian 3190 sputtering apparatus. Generally, this operation is performed in vacuum at a temperature of 100
C. and deposit titanium to a thickness of about 800.degree.

Reference is now made to FIG. In the sectional view of FIG.
A state in which a tantalum silicide (TaSi ₂ ) composite layer 20 is deposited to a thickness of about 500 ° on the substrate is shown. In the preferred embodiment, the tantalum silicide layer is formed by sputtering in situ over the titanium layer. The substrate 10
When depositing both the titanium layer 18 and the tantalum silicide layer 20, they are placed in a vacuum sputtering apparatus. In this embodiment, first, the substrate is put into the sputtering apparatus, and then,
A conventional cleaning process called back sputtering is performed on the upper surface of the poly layer 16. Two targets are placed in the sputtering device. One is titanium, a refractory metal, and the other is a tantalum silicide composite material. Generally, tantalum silicide composites are rich in silicon. In other words, the stoichiometry of this compound is TaSi _x
(X varies between 2 and 3), and therefore these 2
The ratio of the two elements is slightly over 2: 1. Next, after the sputtering apparatus is evacuated, the titanium layer 18 is deposited by sputtering at a temperature of about 100 ° C. The amount of titanium deposited is a function of the setting of the control conditions of the device and the deposition time. After this operation, the second target, tantalum silicide, is selected, the temperature is set to about 400 ° C., and the deposition is performed in the same manner.

It should be understood that it is not necessary to deposit titanium and tantalum silicide in the same manner. For example, titanium can be deposited by another method, e.g., vapor deposition, or in a separate sputtering device, and then the substrate can be placed in a sputtering device for tantalum silicide deposition. Of course, in this case, it is necessary to perform cleaning by back sputtering before depositing tantalum silicide.

After depositing the tantalum silicide composite layer 20, the substrate is removed from the sputtering apparatus, and a photoresist layer is spin-coated on the substrate. The photoresist layer is patterned to define a conductive structure. This conductive structure is the gate of the MOS transistor in this embodiment. Next, plasma etching is performed on the substrate. This etching removes the unpatterned regions, leaving a multilayer polycide structure consisting of a patterned tantalum silicide layer 20, a patterned titanium layer 18, a patterned poly layer 16, and a patterned gate oxide layer 14. Stipulated. This is shown in FIG. This drawing is a perspective view of the gate of the MOS transistor.
It can be seen that the gate of the transistor extends up the field oxide layer 12 and is connected to other circuits.

Generally, the etching of polycide is by dry etching (plasma etching or reactive ion etching), a method that has been used for many years to etch polysilicon and form gates and / or interconnect levels of integrated circuits. . The chemistry for anisotropically etching polycrystalline silicon at a superior etch rate than silicon dioxide is well known. Furthermore, polycide etching methods are well known. This type of etching is mainly used to define vertical edges in the patterned structure. One method of etching polycide was introduced on April 21, 1987 by Fuller.
U.S. Pat.
No. 4,659,426. Another method was 1987 4
No. 4,657,628, entitled "Method of Patterning Local Interconnects", issued to Holloway on May 14, 2009.

After patterning the polycide structure,
Perform isothermal annealing for a short time in N ₂ atmosphere. In the preferred embodiment, this is a two-step process. First, the substrate is brought to a temperature of 550-650 ° C. for about one minute. Next, the temperature of the substrate 10 on which the polycide structure is defined is set to 800 to 900 ° C., typically 900 ° C. for about 20 seconds. The purpose of this anneal is to convert the titanium in the titanium layer 18 to titanium silicide by consuming a portion of the underlying poly layer 16. This method of forming titanium silicide is a conventionally known method.

During the silicide formation process, the titanium layer 18 consumes about 1,500-2,000Å of silicon in the underlying poly layer 16. As shown in FIG. 5, this results in a titanium silicide layer 22 having a thickness of about 2,000 mm. Poly layer 1
6 is left as a layer 16 'about 1500 mm thick.

The purpose of bringing the substrate to a temperature of 550-650 ° C. for one minute is to minimize grain boundary diffusion during the silicide formation process. In this way, N ₂ passes through the grain boundaries and delays grain boundary diffusion. As a result, the silicide formation process at a temperature of 900 ° C. is relatively slow and smooth as compared to a normal silicide formation process. Because the silicide formation process is relatively fast, spikes can occur at the polycide / oxide and gate oxide 14 interface. This is an undesirable result, but processing at a temperature of 550-650 ° C. somewhat delays the occurrence of spikes. Silicide is formed at a temperature of 900 ° C.

In the preferred embodiment, titanium silicide is formed adjacent to the polysilicon after the patterning and etching steps, but the substrate is etched before etching and patterning.
It should be understood that it is possible to raise the temperature to above 850-900 ° C. and to silicide before patterning. Further, titanium silicide can be formed before depositing tantalum silicide. It is only important that the tantalum silicide layer 20 be formed on the titanium silicide layer 22 of the resulting product.

Although tantalum silicide layer 20 is a high melting point silicide material, it differs from silicon silicide in that it has better resistance to oxidation. This is one of the important features of the present invention. However, depositing the tantalum silicide layer 20 directly on the poly layer 16 to form the first conductive coating is less desirable than with titanium silicide.
This is because titanium silicide has a lower resistance than tantalum silicide. Depending on the refractory metal silicide used for layer 20, which is the "covering" layer, the properties of this layer differ. All that matters is that the titanium silicide layer 22 has better resistance to oxidation. Therefore, the titanium silicide layer 22 is selected to minimize sheet resistance and the layer 20
Is selected for maximum resistance to oxidation and optimal chemical stability for subsequent processing.

Without using the structure of the present invention, a compromise would have to be made between chemical stability, resistance to oxidation, and conductivity. By using the method of the present invention, a low resistance layer can be realized using a high melting point metal silicide, and the chemical stability and the resistance to oxidation can be prevented. Next, the second coating layer is selected from refractory metal silicides mainly in view of chemical stability and resistance to oxidation. This provides a very oxidation-resistant surface while utilizing the stability of the refractory metal silicide during operations such as forming the interlayer oxide at temperatures above 800 ° C during the processing stage. There is a technical advantage that you can. This is important for forming a contact from the metallization layer to the tantalum silicide layer or coating layer 20. Forming an oxide on this layer 20 is undesirable because it increases contact resistance.

After forming the polycide gate structure of FIG. 5, the process is completed by forming a transistor. This is achieved using conventional methods. The source / drain is formed by implanting an N-type impurity such as phosphorus or arsenic into the substrate on each side of the patterned polycide gate. As a result, a source 24 and a drain 26 are formed on each side of the gate structure. Channel area
28 is the gate oxide layer between the source 24 and the drain 26
Formed under 14. This structure is shown in FIG.

Reference is now made to FIG. After forming the source 24 and the drain 26, an interlayer oxide layer 30 is deposited on the substrate to form an insulating layer. An opening 32 is formed over the source 24 and an opening 34
Is formed on the drain 26, and the opening 36 is formed on the layer of the gate structure.
Form on top of 20. In the sectional view shown in FIG.
Are on the same cross-section as openings 32 and 34, but generally deviate from these openings 32 and 34
It is necessary to understand that it exists above.

After forming the openings 32, 34, 36, a source contact or plug 38 is formed in the opening 32, a drain plug 40 is formed in the opening 34, and a gate plug 42 is formed in the opening 36. In contact with the underlying conductive structure. The plugs 38, 40, and 42 can be formed by depositing polycrystalline silicon or tungsten by a CVD method. After this operation, a metallized layer such as aluminum is deposited on the upper surface of the interlayer oxide layer 30 and patterned. This metallization layer constitutes one metallization level.

In summary, here has been described a method for forming a polycide structure comprising a titanium silicide layer on a polycrystalline silicon layer and a gate oxide layer. Next, a coating layer, a tantalum silicide or refractory metal silicide layer that is more resistant to oxidation and more chemically stable, is formed over the titanium silicide layer. In this method, a titanium layer is first formed on a polycrystalline silicon layer, and then a tantalum silicide layer is deposited. Next, the multilayer polycide structure is patterned, etched and annealed to form titanium silicide from titanium and the underlying polycrystalline silicon.

Although the present invention has been described in detail with reference to one embodiment, various modifications to the present invention can be made without departing from the spirit and scope of the present invention as defined in the appended claims.
Substitutions and modifications can be made.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor substrate having a polycrystalline silicon layer and an associated gate oxide layer formed on a surface. FIG. 2 is a sectional view showing a state in which a titanium layer is deposited on the structure of FIG. FIG. 3 is a sectional view showing a state in which a tantalum silicide composite layer is formed on the structure of FIG. FIG. 4 is a perspective view of the structure of FIG. 3 after patterning the polycide layer. FIG. 5 is a cross-sectional view of the structure of FIG. 4 in which titanium is converted into silicide. FIG. 6 is a diagram of the completed transistor. (Main reference numbers) 10 ... substrate, 12 ... field oxide layer, 14 ... gate oxide layer, 16 ... polycrystalline silicon layer (poly layer), 18 ... refractory metal layer (titanium layer) , 20 ...... Tantalum silicide layer, 22 ...... Titanium silicide layer, 24 ...... Source, 26 ...... Drain, 28 ...... Channel region, 30 ...... Interlayer oxide layer, 32, 34, 36 ...... Opening , 38, 40, 42 ... plug

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/336 H01L 21/88 R 29/43 29/46 T 29/78 29/78 301G 301P (72) Inventor Robert Otis Miller U.S.A. Texas The Colony Waden Street 5523 (56) References JP-A-60-192371 (JP, A) JP-A-64-17470 (JP, A) JP-A-63-12152 (JP, A) JP-A 62 -249416 (JP, A) JP-A-62-67870 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/28 H01L 21/88 H01L 29/46 H01L 29/78 301

Claims (7)

(57) [Claims] 1. A polycrystalline silicon layer (16) is formed on a substrate (10), and (b) a titanium silicide layer (22) having the same shape as the polycrystalline silicon layer is formed on the polycrystalline silicon layer. And (c) forming a refractory metal silicide layer (20) on the titanium silicide layer which is chemically more stable than titanium silicide, has higher oxidation resistance, and has the same shape as the titanium silicide layer. Forming a conductive structure on a semiconductor substrate, comprising forming and then patterning and etching the substrate to form a conductive structure, wherein the step (b) comprises the following steps (1) and (2): (1) forming a titanium layer on the polycrystalline silicon layer (16),
Annealing is performed at a first temperature slightly lower than the reaction temperature between titanium and polycrystalline silicon under conditions where titanium silicide is not formed, and then (2) titanium reacts with polycrystalline silicon to form titanium silicide. Heating to a second temperature sufficient to perform the heat treatment in two steps. 2. The method according to claim 1, wherein the refractory metal silicide is tantalum silicide. 3. A method according to claim 1, wherein a titanium layer is sputtered on the polycrystalline silicon layer on the substrate, and then a refractory metal silicide layer is sputtered on the titanium layer to form a titanium layer and a refractory metal silicide layer. Item 3. The method according to Item 1 or 2. 4. The method of claim 3 wherein the refractory metal silicide layer is sputtered in the same apparatus as the titanium layer was sputtered. 5. The method according to claim 1, wherein the step of reacting titanium with the polycrystalline silicon layer is performed in a nitrogen atmosphere. 6. The method according to claim 1, wherein polycrystalline silicon is deposited to a predetermined thickness by a CVD method to form a polycrystalline silicon layer. 7. The method according to claim 1, further comprising forming an oxide layer on the substrate before forming the polycrystalline silicon layer.