JPS60176179U - Pulse period discrimination circuit - Google Patents
Pulse period discrimination circuitInfo
- Publication number
- JPS60176179U JPS60176179U JP6424984U JP6424984U JPS60176179U JP S60176179 U JPS60176179 U JP S60176179U JP 6424984 U JP6424984 U JP 6424984U JP 6424984 U JP6424984 U JP 6424984U JP S60176179 U JPS60176179 U JP S60176179U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- signal
- pulse period
- flip
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるパルス周期判別回路の一実施例を
示す回路図、第２図ａ ％ ｆは第１図に示す回路の各
部動作波形図である。
１・・・・・・発振回路、２・・・・・・カウンタ、３
，４・・・・・・第１、第２フリップフロップ回路。FIG. 1 is a circuit diagram showing an embodiment of a pulse period discrimination circuit according to the present invention, and FIG. 2 a % f is a waveform diagram showing the operation of each part of the circuit shown in FIG. 1. 1...Oscillation circuit, 2...Counter, 3
, 4...first and second flip-flop circuits.
Claims (1)
の計数を行なうことにより、基準周期に対応した計数値
に達すると出力信号を発生するカウンタと、このカウン
タの出力信号をセット入力とするとともに入力パルス信
号の供給時にそのリセット出力信号をデータとして取り
込む第１フリップフロップ回路と、前記カウンタの出力
信号によってセットされるとともに前記第２フリップフ
ロップ回路のセット出力によりリセットされることによ
って入力パルス信号に対する周期の判別結果を出力する
第２フリップフロップ回路とを備えたパルス周期判別回
路。A counter that is reset by an input pulse signal and counts the reference clock signal, and generates an output signal when the count value corresponding to the reference period is reached, and the output signal of this counter is used as a set input, and the output signal of the input pulse signal is A first flip-flop circuit that takes in the reset output signal as data when supplied, and a result of determining the period for the input pulse signal by being set by the output signal of the counter and being reset by the set output of the second flip-flop circuit. a second flip-flop circuit that outputs a pulse period determination circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6424984U JPS60176179U (en) | 1984-04-30 | 1984-04-30 | Pulse period discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6424984U JPS60176179U (en) | 1984-04-30 | 1984-04-30 | Pulse period discrimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60176179U true JPS60176179U (en) | 1985-11-21 |
Family
ID=30595158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6424984U Pending JPS60176179U (en) | 1984-04-30 | 1984-04-30 | Pulse period discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60176179U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55417A (en) * | 1978-05-23 | 1980-01-05 | Fujitsu Ltd | Frequency comparator circuit |
-
1984
- 1984-04-30 JP JP6424984U patent/JPS60176179U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55417A (en) * | 1978-05-23 | 1980-01-05 | Fujitsu Ltd | Frequency comparator circuit |
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