JPS583641U - pulse delay circuit - Google Patents
pulse delay circuitInfo
- Publication number
- JPS583641U JPS583641U JP9812281U JP9812281U JPS583641U JP S583641 U JPS583641 U JP S583641U JP 9812281 U JP9812281 U JP 9812281U JP 9812281 U JP9812281 U JP 9812281U JP S583641 U JPS583641 U JP S583641U
- Authority
- JP
- Japan
- Prior art keywords
- output
- delay circuit
- clock pulse
- pulse delay
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のパルス遅延回路の一例を示すブ白ツク図
、第２図は本考案にかかるパルス遅延回路の一実施例を
示す基本構成のブロック図、第３図ａ乃至ｄは第１図の
動作に供する各部の波形図、第４図ａ乃’Ｍｃは第２図
の動作に供する各部の波形図である。 ′−
１０・・・・・・パルス発振器、′１１・・・・・・バ
イナリカウンタ、１２・・・・・・ディジタル比較器、
１３・・・・・・プログラマブル設定器。 ・FIG. 1 is a blank diagram showing an example of a conventional pulse delay circuit, FIG. 2 is a block diagram of the basic configuration of an embodiment of the pulse delay circuit according to the present invention, and FIGS. 4A to 4' are waveform diagrams of various parts used for the operation shown in FIG. 2. FIGS. '- 10...Pulse oscillator, '11...Binary counter, 12...Digital comparator,
13...Programmable setting device.・
Claims (1)
リア信号を基準のクロックパルスとして発生するカウン
タと、任意の数値出力を設定可能なプログラマブル設定
器と、前記カウンタの計数出力と前記設定器の数値出力
を前記基準のクロックパルスを基にして比較し、その各
出力値が一致したときに得られる前記設定値に設定され
た数値出力の時間だけ遅延したクロックパルスを発生す
るディジタル比較器とからなるパルス遅延回路。A counter that counts clock pulses and generates a carrier signal synchronized with the input pulse as a reference clock pulse, a programmable setting device that can set any numerical output, and a count output of the counter and a numerical output of the setting device. and a digital comparator that generates a clock pulse delayed by the time of the numerical output set to the set value obtained when the respective output values match based on the reference clock pulse. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9812281U JPS583641U (en) | 1981-06-30 | 1981-06-30 | pulse delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9812281U JPS583641U (en) | 1981-06-30 | 1981-06-30 | pulse delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS583641U true JPS583641U (en) | 1983-01-11 |
Family
ID=29892890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9812281U Pending JPS583641U (en) | 1981-06-30 | 1981-06-30 | pulse delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583641U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01216617A (en) * | 1988-02-24 | 1989-08-30 | Nippon Telegr & Teleph Corp <Ntt> | Timing generator |
| JPH02262769A (en) * | 1990-03-08 | 1990-10-25 | Canon Inc | Color picture recorder |
-
1981
- 1981-06-30 JP JP9812281U patent/JPS583641U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01216617A (en) * | 1988-02-24 | 1989-08-30 | Nippon Telegr & Teleph Corp <Ntt> | Timing generator |
| JPH02262769A (en) * | 1990-03-08 | 1990-10-25 | Canon Inc | Color picture recorder |
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