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JPS59119649U - Periodic pulse train extraction circuit - Google Patents

Periodic pulse train extraction circuit

Info

Publication number
JPS59119649U
JPS59119649U JP1357083U JP1357083U JPS59119649U JP S59119649 U JPS59119649 U JP S59119649U JP 1357083 U JP1357083 U JP 1357083U JP 1357083 U JP1357083 U JP 1357083U JP S59119649 U JPS59119649 U JP S59119649U
Authority
JP
Japan
Prior art keywords
pulse train
circuit
periodic pulse
periodic
extraction circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1357083U
Other languages
Japanese (ja)
Inventor
勝 青木
Original Assignee
八重洲無線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 八重洲無線株式会社 filed Critical 八重洲無線株式会社
Priority to JP1357083U priority Critical patent/JPS59119649U/en
Publication of JPS59119649U publication Critical patent/JPS59119649U/en
Pending legal-status Critical Current

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  • Networks Using Active Elements (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の構成を示すプロ゛ツク図、第2図はそ
の動作の説明図、第3図は遅延回路の構成例である。 D□・・・遅延回路、P・・・定周期性パルス、p・・
・非周期性パルス。
FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is an explanatory diagram of its operation, and FIG. 3 is an example of the configuration of a delay circuit. D□...delay circuit, P...periodic pulse, p...
・Aperiodic pulse.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周期性のパルス列と非周期性のパルスの混在する信号を
AND回路の一方の入力に加えると共に、同一信号を遅
延回路を通して前記AND回路の他方の入力に加え、前
記遅延回路の遅延時間を周期性パルス列の周期と等しく
設定することによりAND回路出力に周期性パルス列の
みを出力する定周期性パルス列抽出回路。
A signal containing a mixture of periodic pulse trains and non-periodic pulses is applied to one input of the AND circuit, and the same signal is applied to the other input of the AND circuit through a delay circuit, so that the delay time of the delay circuit becomes periodic. A constant periodic pulse train extraction circuit that outputs only a periodic pulse train to the AND circuit output by setting the period equal to the period of the pulse train.
JP1357083U 1983-02-01 1983-02-01 Periodic pulse train extraction circuit Pending JPS59119649U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1357083U JPS59119649U (en) 1983-02-01 1983-02-01 Periodic pulse train extraction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1357083U JPS59119649U (en) 1983-02-01 1983-02-01 Periodic pulse train extraction circuit

Publications (1)

Publication Number Publication Date
JPS59119649U true JPS59119649U (en) 1984-08-13

Family

ID=30144956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1357083U Pending JPS59119649U (en) 1983-02-01 1983-02-01 Periodic pulse train extraction circuit

Country Status (1)

Country Link
JP (1) JPS59119649U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115362A (en) * 1974-07-29 1976-02-06 Tokyo Keiki Kk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115362A (en) * 1974-07-29 1976-02-06 Tokyo Keiki Kk

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