JPS5877943U - Multi-point sampling circuit - Google Patents
Multi-point sampling circuitInfo
- Publication number
- JPS5877943U JPS5877943U JP17212281U JP17212281U JPS5877943U JP S5877943 U JPS5877943 U JP S5877943U JP 17212281 U JP17212281 U JP 17212281U JP 17212281 U JP17212281 U JP 17212281U JP S5877943 U JPS5877943 U JP S5877943U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- point sampling
- sampling circuit
- flip
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 title claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来の多数点サンプリング回路の一例を示す
ブロック図、第２図は本考案の一実施例のブロック図で
ある。
Ａ・・・・・・カウンタ、１，４・・・・・・ＡＮＤゲ
ート、２・・・・・・計数回路、３・・・・・・判定回
路、１２・・・・・・ＥＸ−ＯＲ回路、１３・・・・・
・フリップフロップ回路。FIG. 1 is a block diagram showing an example of a conventional multi-point sampling circuit, and FIG. 2 is a block diagram of an embodiment of the present invention. A... Counter, 1, 4... AND gate, 2... Counting circuit, 3... Judgment circuit, 12... EX- OR circuit, 13...
・Flip-flop circuit.
Claims (1)
タを記憶するフリップフロップ回路と、該ラリツブフロ
ップ回路の出力信号と入力信号との排他的論理和をとる
ＥＸ−ＯＲ回路と該ＥＸ−ＯＲ回路の出力信号によって
ゲート制御されたサンプリングクロックの数を計数し、
その計数結果に基づいて前記フリップフロップ回路の状
態を制御するカウンタとを具備したことを特徴とする多
数点サンプリング回路。In a multi-point sampling circuit, a flip-flop circuit that stores outputted digital data, an EX-OR circuit that takes an exclusive OR of the output signal of the Laritub-flop circuit and an input signal, and an output signal of the EX-OR circuit. Count the number of sampling clocks gated by
A multi-point sampling circuit comprising: a counter that controls the state of the flip-flop circuit based on the counting result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17212281U JPS5877943U (en) | 1981-11-20 | 1981-11-20 | Multi-point sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17212281U JPS5877943U (en) | 1981-11-20 | 1981-11-20 | Multi-point sampling circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5877943U true JPS5877943U (en) | 1983-05-26 |
Family
ID=29964029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17212281U Pending JPS5877943U (en) | 1981-11-20 | 1981-11-20 | Multi-point sampling circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5877943U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH043638A (en) * | 1990-04-20 | 1992-01-08 | Toko Denki Kk | Transmission signal demodulation method and device |
-
1981
- 1981-11-20 JP JP17212281U patent/JPS5877943U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH043638A (en) * | 1990-04-20 | 1992-01-08 | Toko Denki Kk | Transmission signal demodulation method and device |
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