JPS6012766A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To keep a low resistance value even in the presence of inclination of a wiring layer by a method wherein a III-V group semiconductor layer is grown on recess and mesa parts formed in a semi-insulation III-V group compound substrate, where semiconductor elements are formed, and then an N<+> type III-V group semiconductor layer containing Sn and N type impurity is used in connection of the recess part to the mesa part by means of a wiring layer. CONSTITUTION:The semi-insulation GaAs substrate 1 is etched by the adoption of a normal photo lithography technique, resulting in the formation of the recesses R and mesas M. Next an N<+> type GaAs layer 2 is grown over the entire surface including these by a molecular ray epitaxial method, where the semiconductor elements are formed, and the layer 2 is used also as the wiring layer for these elements. In this construction, the layer 2 is formed of a semiconductor containing Sn, having the impurity concentration at about 5X10<18>/cm<3>, and electrodes 3 and 4 are mounted on a mesa M and a recess R, respectively. The thickness of the layer in the part of inclination is made nearly equal to that in the other part in such a manner, so that the resistance value does not increase.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device having a wiring layer mainly made of an nr-v group compound semiconductor and having extremely good electrical conductivity.

Prior Art and Problems In recent years, development and research related to '1kII integration and higher performance of optical integrated circuits have been active.

Generally, compound semiconductors are used as materials constituting optical integrated circuits, and tU-V group compound semiconductors are also one of the important materials.

In an optical integrated circuit using this nr-v group compound semiconductor, for example, as shown in FIG.
After forming a recess portion R and a mesa portion M on a substrate L, molecular beam epitaxial growth (MBE) is performed.
2. Description of the Related Art A semiconductor layer is grown using a beam epitaxy method, and devices are exploded into the semiconductor layer.

In that case, a thick semiconductor layer is grown in the recessed portion R, and a relatively thin semiconductor layer is grown in the mesa portion M, respectively, to form a substantially flat surface as a whole. diode(
In addition, in the mesa portion M, field effect transistors and the like that drive the optical elements are formed.

The reason for doing this is that optical circuits usually require a thick semiconductor layer, and electronic circuits are formed on relatively thin semiconductor layers, so optical integrated circuits that include these In this case, the surface flatness is lost, making it difficult to apply photolithography technology. Therefore, a thick semiconductor layer is formed in the recessed portion R, and a thin semiconductor layer is formed in the mesa portion M.
It forms.

By the way, the semiconductor layer of the recessed portion R and the semiconductor layer of the mesa portion M must be connected by a wiring layer having electrical conductivity, and the wiring layer is usually considered to be:
For example, it is an n+ type GaAs layer containing silicon (St) at a high concentration as an n type impurity. However, this n+
When a type GaAs layer is grown by the MB2 method, the layer formed on the slope of the recess portion R or mesa portion M exhibits an extremely high resistance value and cannot be used as a side bottom or wiring.

In this way, the St-containing GaAs grown on the inclined surface
The reason why j@ has high resistance is currently unknown.

However, since the electrical conductivity is good even though it is grown on a flat part, if the slope of the recess part R or mesa part M is made gentle, the above-mentioned drawbacks may not occur. The typical technique currently in use for forming the portion R or mesa portion M is chemical etching, and when this technique is used, the slope angle of the recess portion R or mesa portion M is limited to some extent. Therefore, it cannot be selected arbitrarily.

OBJECTS OF THE INVENTION The present invention provides a semiconductor device having a wiring layer made of an m-v group compound semiconductor that has good electrical conductivity even when extended on an inclined surface of a recessed portion or a mesa portion.

Structure of the Invention In the present invention, in a semiconductor device in which various elements are formed in a ■-V group compound semiconductor layer in a recess portion and a mesa portion formed on a semi-insulating m-V group compound substrate, the recess portion and n to connect the ■-■ group compound semiconductor layer in the mesa part.
A wiring layer made of an n+ type, m-v group compound semiconductor layer containing tin as a type impurity is formed.

Even if the wiring layer extending from the n4'' type ■-■ group compound semiconductor layer containing tin as an impurity is formed on the sloped surfaces of the recess portion and mesa portion, its electrical conductivity is not impaired at all. Although the reason for this is not clear, it is easy to confirm this effect experimentally.

Embodiment of the Invention As shown in FIG. 1, a recess portion 17 and a mesa portion M are formed by etching a semi-insulating GaAs substrate 1 using ordinary photolithography techniques.

As seen in the second i111, an n+ type GaAs semiconductor layer 2 is grown by applying the MB2 method to the semi-insulating GaAs substrate 1 processed as described above. The conditions at this time are as follows.

Growth temperature +600 ('C) Growth rate: 1.5 (μm/hour) Film thickness: 4 [μm] (in flat region) N-type impurity: Tin (Sn) Impurity concentration: 5 x 10''(011-') In the n+ type GaAs semiconductor layer 2 grown as described above, electrodes 3 and 4 were formed in the mesa portion M and the recessed portion R, and the resistance value between them was measured. The resistance was 5×IG-3 (Ω·1).It was confirmed that this specific resistance was inversely proportional to the impurity concentration.

Effects of the Invention In the semiconductor device of the present invention, a wiring connecting the at-V group compound semiconductor layer formed in the recessed portion and the mesa portion of the m-v group compound substrate having the recessed portion and the mesa portion is provided.
By using a ■-V group compound semiconductor containing Sn as the t-layer, the wiring layer exists on the inclined surface of the recessed portion or mesa portion, and a low resistance value can be maintained, for example. , when the semiconductor device is an optical integrated circuit, is particularly effective in promoting high integration.

[Brief explanation of the drawing]

Figure 1 shows a semi-insulating G with a recessed part and a mesa part.
FIG. 2 is a perspective view of the main part of the a As substrate, and FIG. 2 is a fresh side view of the main part of the embodiment of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2nd n+ type Q a As semiconductor layer (wiring layer), 3rd and 4th electrodes, R is a recessed portion, and M is a mesa portion. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani (1 other person)

Claims (1)

[Claims] In a semiconductor device in which a nr-v group compound semiconductor layer is grown in a recess portion and a mesa portion formed on a semi-insulating ■-■ group compound substrate, and various elements are formed on the nr-v group compound semiconductor layer. and nr of the recessed part and mesa part.
- A semiconductor device comprising a wiring layer made of an n+ type m-■ group compound semiconductor layer containing tin as an n-type impurity to connect the V group compound semiconductor layers.