JP2583793B2 - Semiconductor substrate - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor substrate used for a high-speed electronic device, a light-emitting device, a light-receiving device, and the like.

(2) Conventional technology and its problems With the demand for multifunctional and high-speed semiconductor devices, the performance of integrated circuits in which a plurality of devices are arranged on the same substrate has been promoted. However, in an integrated circuit in which a plurality of devices are arranged on the same substrate, devices are formed only on the upper portion of the substrate and partially, so that not only external regions such as the lower portion of the device but also between the devices become unnecessary, and the electrode This also hinders electrical insulation between devices or between devices, and as a result, parasitic elements such as parasitic impedance are generated in the integrated circuit, which is a major problem in improving the performance of the integrated circuit.

Methods conventionally used to maintain the insulation of the region outside the device include increasing the purity of the substrate crystal or increasing the resistance by impurity doping, increasing the resistance of the region outside the device by impurity doping using ion implantation, and improving the dryness. There is a method of removing a region outside the device by etching or wet etching. However, this method requires an advanced crystal growth technique, and it is essentially impossible to maintain perfect insulation with a semiconductor having a small band gap even if the advanced crystal technique is used.
Is a method in which a deep level is formed in a region outside the device by utilizing the selectivity of the region possessed by ion implantation, or the region is made amorphous to increase the resistance. In ion implantation, for example, a lower region of the device is formed. When the resistance is increased, damage to the device region cannot be avoided. In the method (1), a step is generated between the device region and the outside device region, which causes difficult problems such as defocus in photolithography and disconnection of wiring between devices.

(3) Object of the Invention It is an object of the present invention to provide a semiconductor substrate in which the area outside the device in an integrated circuit has a sufficiently high resistance.

(4) Constitution of the invention (4-1) Difference between the features of the invention and the prior art In the present invention, an impurity region having a conductivity type opposite to that of an outer region is formed in a portion adjacent to a region to be increased in resistance. The most important feature is that both regions are depleted and have high resistance by utilizing a built-in voltage generated by the difference in the conductivity type of the regions. Therefore, there are no problems such as the necessity of a crystal having extremely high purity, damage to a device, and a step described above.

(4-2) Example [Example 1] FIG. 1 is a cross-sectional view of a junction field effect transistor and its substrate for explaining a first example of the present invention, wherein 1 is a semi-insulating InP substrate, Is the characteristic thickness d _A of the present invention,
InP layer with p-type impurity concentration N _A ⁺ , 3 is high purity In _{0.53 with} thickness d _D
Ga _0.47 As layer, 4 is an n-type In _0.53 Ga _0.47 As impurity layer serving as an active layer of a junction field effect transistor, and 5 is an n-type In _0.53 Ga
_0.47 p-type In formed by ion implantation into As impurity layer 4
_{A 0.53} Ga _0.47 As impurity region, 6 is a gate electrode, and 7, 8 are a source electrode and a drain electrode, respectively. Here, the region 3 which is an out-of-device region is a buffer layer for improving the crystallinity of the region 4 and uses a high-purity In _0.53 Ga _0.47 As epitaxial growth technique, and is usually about 10 ¹⁴ to 10 ¹⁵ cm ^-3. N-type conductive carrier.

In order to completely deplete the regions 2 and 3, as exemplified below, d _A in those of the limited length d _D ^+, d _A
Must be selected appropriately. Figure 2 shows high purity In _0.53 Ga _0.47 As
The conductive carrier density of the layer 3 as N _D, Figure 1 Oite A-
The horizontal axis represents the distance from the interface between the regions 1 and 2 along the line A ', and the conductive carrier concentration is shown. Here, in order to completely deplete regions 2 and 3, the limit on d _D is approximately , And the ⁺ under N _A of this limitation, it is necessary to choose the d _A so as to satisfy N _A ⁺ d _A = N _D d _D and N _A ⁺ »N _D. Here, q is an elementary charge, ε ₀ is a vacuum dielectric constant, and ε _r is a region 3 (In _0.53 Ga
Dielectric constant of _0.47 As), E ₂₀ is the difference between the conduction band bottom and the Fermi level of the region 2 (InP), E ₃₀ is region 3 (In _0.53 Ga
_0.47 As) Difference between conduction band bottom and Fermi level, ΔE ₀
Is the conduction band discontinuity between region 2 (InP) and region 3 (In _0.53 Ga _0.47 As). The values for these parameters are
This is illustrated in FIG. For simplicity, the case where the carrier concentration distribution in the p-type impurity layer 2 is constant has been described as an example. However, even when the p-type impurity layer 2 is formed by, for example, ion implantation and the conductive carrier concentration is distributed in the depth direction, the same applies. Can be determined. For example N _D using the above formula is 1
When × 10 ¹⁵ cm ^-3 and d _D are 0.5 μm, N _A ⁺ and d _A are each 1
Regions 2 and 3 can be completely depleted by selecting × 10 ⁷ cm ⁻³ and 5 nm. By providing the region 2, the region 3 is depleted, a leakage current flowing through the region 3 is prevented, and a high-performance field-effect transistor can be realized.

This structure was formed on a semi-insulating InP substrate by MOVPE.
The MOVPE formation condition is 0.1 atm.
The growth time was about 30 seconds without adding impurities in the area 3 and the growth time was about 10 minutes in the area 4 by adding Si as an impurity. The thickness of the region 4 is about 0.2 μm.

The region 5 has a thickness of about 0.1 μm, and after forming the regions 2, 3, and 4, Zn ions are applied at a voltage of 180 k in an atmosphere of a degree of vacuum of 10 ⁻⁶ Torr.
The implantation is performed for 1 minute at eV, and then activation annealing at about 700 ° C. is performed to form a p-type conductive carrier layer. 6 is AuZnNi (50 nm) formed on the region 5
/ Au (150 nm) gate electrode, 7 and 8 are AuGeNi (50 nm) / Au (15
0 nm) Source and drain electrodes.

In the example of FIG. 1, In _0.53 Ga _0.47 As is formed by the MOVPE method, but may be formed by the MBE method, the LPE method, or the like, and this is the same in Examples 2, 3, 4, and 5 described below. . Particularly, the region 2 can also be formed by ion implantation of a p-type impurity or diffusion of a p-type impurity on a semi-insulating InP substrate. The semi-insulating substrate 1, the p-type impurity layer 2, the high-purity layer 3, and the n-type impurity layer 4 are made of InP, In _0.53 Ga _0.47 As.
Besides, non-polar semiconductors such as Si and Ge, GaAs, InAs, AlAs, GaP
Binary semiconductors such as Al _x Ga _{1 -x} As (0 <x <
Ternary compound semiconductor such as 1), In _x Ga _1-x As _y P _1-y (0 <x, y
It is also possible to use a quaternary compound semiconductor such as <1). Further, the region 2 can be made of the same semiconductor as the region 3. Further, even when the region 3 is a superlattice made of various kinds of semiconductors, the region 2 can be completely depleted.

Embodiment 2 FIG. 3 is a view for explaining a second embodiment of the present invention.
This is an example in which the thickness of the In _0.53 Ga _0.47 As buffer layer in the first embodiment is further increased in order to further improve the crystallinity of the field effect transistor active layer. Region 9 is semi-insulating
An InP substrate, regions 10, 12 each characteristic thickness to the present invention _{d A, 2d A, 2d A} , In the p-type impurity concentration of 1 × 10 ¹⁷ cm ^-3
_0.53 Ga _0.47 As layer, regions 11, 13 and 15 are 2d _D and 2d respectively
High purity In _0.53 Ga _{0.47 with D} , d _D , n-type impurity concentration of 1 × 10 ¹⁵ cm ^-3
The As layer and the region 16 are an n-type In _0.53 Ga _0.47 As impurity layer serving as an active layer of the junction field effect transistor.
It is formed by E method. Region 17 is a p-type In _0.53 Ga _0.47 formed by ion implantation into an n-type In _0.53 Ga _0.47 As impurity layer.
As impurity region, 18 is a gate electrode, 19 and 20 are a source electrode and a drain electrode, respectively. The method of forming each part is the same as in the first embodiment. Where d _A and d _D are the areas in the first embodiment.
2, 3 were determined using the above-described calculation formula assuming that In _0.53 Ga _0.47 As was obtained, and thereby, 10, 11, 12, 1, 1
Areas 3, 14, and 15 are completely depleted.

FIG. 3 shows an example in which three p-type impurity layers are used. However, the p-type impurity layers and the n-type impurity layers are alternately d _A , 2d _D , 2d _A , 2
It is also possible to stack multiple layers of d _D …, 2d _A , 2d _D , 2d _A , d _D and completely deplete all these layers. The semi-insulating substrate 9, the p-type impurity layers 10, 12, and 14, the high-purity layers 11, 13, and 15, and the n-type impurity layer 16 can also be semiconductors other than InP and In _0.53 Ga _0.47 As.

Third Embodiment FIG. 4 is a cross-sectional view of an integrated circuit of a pin type photodiode and a junction field effect transistor according to a third embodiment of the present invention and a substrate thereof, where a is a pin type photodiode, c Is a junction field-effect transistor, b is a region outside the device, and in a, 21 is a semi-insulating InP substrate, and 22 is a semi-insulating
n-type In formed by n-type impurity ion implantation into nP substrate
P region, 23 is 2μm high purity formed by MOVPE method
In _0.53 Ga _0.47 As region, 24 is an n-type In _0.53 Ga formed by implanting n-type impurity ions into a high-purity In _0.53 Ga _0.47 As region.
_{In the 0.47} As region, 25 is a 0.1 μm-thick p-type In _0.53 G formed by implanting p-type impurity ions into the high-purity In _0.53 Ga _0.47 As layer.
a _0.47 As region, 26: AuZnNi (50 nm) / Au formed on 25
A (150 nm) pin-type photodiode p-electrode 27 is an AuGeNi (50 nm) / Au (150 nm) pin-type photodiode n-electrode formed on 24. Further, in c, 28 is a thickness d _A1 formed by implanting p-type impurity ions into a semi-insulating InP substrate, an InP region having a p-type impurity concentration N _A1 ⁺ , 29 is a thickness d formed simultaneously with 23 by MOVPE. _D1 high-purity In _0.53 Ga _0.47 As region, 30 is a 0.5 μm-thick n-type In _0.53 Ga _0.47 As region formed by implanting n-type impurity ions into the high-purity In _0.53 Ga _0.47 As layer, 31 is n-type In _0.53 Ga _0.47 As having a thickness of 0.1μm was formed by p-type impurity ion implantation into the region p-type in _0.53 Ga _0.47 As region, 32
Is an AuZnNi (50 nm) / Au (150 nm) gate electrode formed on 31; 33 and 34 are AuGeNi (50 nm) / Al (150 nm) source electrodes;
It is a drain electrode. Furthermore, in b, 35 is semi-insulating
Thickness d formed by implanting p-type impurity ions into InP substrate
_A2 is an InP region having a p-type impurity concentration of N _A2 ⁺ , and 36 is a high-purity In _0.53 Ga _0.47 As region having a thickness of d _D2 . In this integrated circuit, 23, 24, 25, 29, 30, 31, and 36 are formed in one In _0.53 Ga _0.47 As layer, and the process is shared and the device is flattened.

N _A1 ⁺ , d _A1 in the junction field effect transistor c is changed to N _A
⁺ , d _A can be appropriately selected using the above formula,
Is completely depleted in the same manner as in the first embodiment. However, here, N _A2 ⁺ , d _A2 is also appropriately selected in the same manner using the above-mentioned calculation formula, and the regions 35 and 36 are completely depleted. Is depleted. As a result, the pin-type photodiode a and the junction field-effect transistor c are electrically insulated by the region b outside the device, and a high-performance optoelectronic integrated circuit can be realized.

Although the illustration of FIG. 4 shows an example of the electrical insulation between the electronic device and the optical device, the electrical insulation between the electronic device and the electronic device, the electrical insulation between the optical device and the optical device are illustrated. The case is exactly the same. Region 28 and
35 can also be formed by diffusion of p-type impurities or selective epitaxial growth. Further, the semi-insulating substrate 21 and the regions 22, 23, 24, 25, 28, 29, 30, 31, 35 and 36 are InP and In.
Semiconductors other than _0.53 Ga _0.47 As are also possible. The above application is also possible for the fourth and fifth embodiments described below.
4 shows an example in which the region 35 is formed over the entire device outside region b. However, in order to electrically insulate the device regions a and c, the region 35 is not necessarily formed over the entire device outside region b. This need not be done, and this is the same in the fourth embodiment described below.

Fourth Embodiment FIG. 5 is a diagram for explaining a fourth embodiment of the present invention.
Are a pin-type photodiode and a junction field-effect transistor, respectively, which are exactly the same as those of the embodiment 3 in FIG. e, 37 and 39 are high-purity In _0.53 Ga _0.47 As regions of d _D1 and d _D2 , respectively, having thicknesses formed by the MOVPE method,
_{Reference numeral} 38 denotes a p-type In _0.53 Ga _0.47 As region having a thickness of d _A1 + d _A2 formed by implanting p-type impurity ions into the high-purity In _0.53 Ga _0.47 As layer. The structure shown in FIG. 5 shares one In _0.53 Ga _0.47 As layer in each region, similarly to the third embodiment of FIG. 4, and achieves a common process and a flattened device.

Here, using the above-mentioned calculation formula, N _A1 ⁺ and d _A1 are a part of area 37 and a part of area 38 adjacent thereto (thickness d _A1 ), N _A2 ⁺ and d _A2
Is the area 39 and the remainder of the area 38 adjacent to it (thickness d
_A2 ) is chosen to be completely depleted. Therefore, since the region e outside the device is completely depleted, d
And f are electrically insulated.

Although ion implantation is used to form the region 38 in the example of FIG. 5, when d _D2 = 0, that is, when the region 38 is on the substrate surface, it can be formed by impurity diffusion or epitaxial growth.

Embodiment 5 FIG. 6 is a diagram for explaining a fifth embodiment of the present invention.
The portion i is a pin-type photodiode and a junction field-effect transistor, respectively, which are exactly the same as those of the embodiment 3 in FIG. In h, 40 and 42 are high-purity In _0.53 Ga _0.47 As having widths d _D1 and d _D2 respectively formed by the MOVPE method.
The layer 41 has a width d _A1 + d _A2 formed by implanting p-type impurity ions into the high-purity In _0.53 Ga _0.47 As layer, and a p-type impurity concentration of N _A ⁺ .
n _0.53 Ga _0.47 As region. The structure shown in FIG. 6 shares one In _0.53 Ga _0.47 As layer in each region as in the third embodiment of FIG. 4, and achieves a common process and a flattened device.

Here, using the above formula, N _A ⁺ , d _A1 are a part of area 40 and 41 adjacent thereto (width d _A1 ), and d _A2 is area 42.
And the remaining part (width d _A2 ) of the region 41 adjacent thereto is completely depleted. Therefore, since the region h outside the device is completely depleted, g and i are electrically insulated. Here it is shown an example in which the entire device area outside h is depleted but, even if the d _D1 or the entire device area outside h short distance d _D2 is not depleted, electrically a device region g and i It is possible to insulate.

Although the region 41 is formed by ion implantation in the example of FIG. 6, it can be formed by impurity diffusion.

(5) Effects of the Invention As described above, according to the present invention, the depletion of the region outside the device in the integrated circuit sufficiently increases the resistance, so that the parasitic element such as the parasitic impedance in the integrated circuit is reduced. There is an advantage that generation is suppressed and high performance of the integrated circuit can be achieved.

[Brief description of the drawings]

FIG. 1, FIG. 3, FIG. 4, FIG. 5 and FIG.
FIG. 2 is a cross-sectional view for explaining the third, fourth, and fifth embodiments, FIG. 2 is a diagram showing a conductive carrier concentration distribution in the semiconductor substrate shown in FIG. 1, and FIG. 7 is a characteristic illustrating values of parameters used in the description of the present invention. FIG. 1 ...... semi-insulating InP substrate, 2 p-type impurity concentration N _A ⁺ InP layer at ...... thickness d _A, 3 high-purity In _0.53 Ga _0.47 As of ...... thickness d _D
Layer, 4... N-type In _0.53 Ga _0.47 As impurity layer serving as an active layer of a junction field effect transistor, 5... P-type In _0.53 Ga _0.47
As impurity region, 6 ... gate electrode, 7 ... source electrode,
8 ... Drain electrode, 9 ... Semi-insulating InP substrate, 10 ...
P-type impurity concentration of 1 × 10 ¹⁷ cm ^-3 with a thickness d _A In _0.53 Ga _0.47 As
Layer, 11 a high-purity n-type In _0.53 Ga _0.47 As layer of ...... thickness 2d impurity concentration _D 1 × 10 ¹⁵ cm ^-3, impurity concentration of 1 in 12 ...... thickness 2d _DA
× 10 ¹⁷ p-type In _0.53 Ga _0.47 As layer of cm ^-3, 13 high-purity n-type In _0.53 of ...... impurity concentration in a thickness ^{_{2d D 1 × 10 15 cm -3}} Ga 0.47 As
Layer, 14 ...... thickness 2d impurity concentration _A 1 × 10 ¹⁷ cm ^-3 p-type In
_0.53 Ga _0.47 As layer, 15 ...... thickness d impurity concentration _D 1 × 10 ¹⁵ cm
^-3 high-purity n-type In _0.53 Ga _0.47 As layer, 16 ... n-type In _0.53 Ga
_0.47 As impurity layer, 17 p-type In _0.53 Ga _0.47 As impurity region, 18 gate electrode, 19 source electrode, 20 drain electrode, 21 semi-insulating InP substrate, 22 n-type InP region, 23: High-purity In _0.53 Ga _0.47 As region with a thickness of 2 μm, 24
…… n-type In _0.53 Ga _0.47 As region, 25 …… p-type In _0.53 Ga _0.47
As region, 26: pin-type photodiode p-electrode, 27: pin-type photodiode n-electrode, 28: p-type InP region with thickness d _A1 , 29
…… High purity In _0.53 Ga _0.47 As region of thickness d _D1 , 30 …… n-type I
n _0.53 Ga _0.47 As region, 31 ... p-type In _0.53 Ga _0.47 As region, 3
2 ... Gate electrode, 33 ... Source electrode, 34 ... Drain electrode, 35 ... P-type InP region with thickness d _A2 , 36 ... High-purity In _0.53 Ga _0.47 As region with thickness d _D2 , 37 ... … High purity In of thickness d _D1
0.53 Ga _0.47 As region, 38 p-type In _0.53 Ga of thickness d _A1 + d _A2
0.47 As region, 39 ...... high purity an In _0.53 Ga _0.47 As region of thickness d _D2, 40 high purity an In _0.53 Ga _0.47 As region of ...... width d _D1, 41 ......
A p-type In _0.53 Ga _0.47 As region having a width d _A1 + d _A2 , a high-purity In _0.53 Ga _0.47 As region having a width d _D2 .

Claims (1)

(57) [Claims] An n-type high-purity region made of a first semiconductor which is not doped with an impurity, a p-type impurity region made of a second semiconductor, and an energy gap of the first semiconductor; The size is equal to or smaller than the size of the energy gap of the second semiconductor, q is an elementary charge, ε
₀ is the vacuum dielectric constant, ε _r is the relative dielectric constant of the high-purity region, E ₂₀
The difference between the conduction band bottom and Fermi level of the impurity region, E ₃₀ is the difference between the conduction band bottom and Fermi level of the high-purity region, Delta] E ₀ is the conduction band and the high-purity region and the impurity region discrete values, when N _D is that the carrier concentration of the high purity region, the film thickness d _D of the high-purity region, , And the like that the thickness d _A of the carrier concentration N _A ⁺ and the impurity region of the impurity region under this restriction satisfies ^{_{N A + d A = N D}} d D and N _A ⁺ »N _D A semiconductor substrate, which is selected from the group consisting of: