KR0170486B1 - Fabrication method of double peak resonant tunneling diode - Google Patents
Fabrication method of double peak resonant tunneling diode Download PDFInfo
- Publication number
- KR0170486B1 KR0170486B1 KR1019950050516A KR19950050516A KR0170486B1 KR 0170486 B1 KR0170486 B1 KR 0170486B1 KR 1019950050516 A KR1019950050516 A KR 1019950050516A KR 19950050516 A KR19950050516 A KR 19950050516A KR 0170486 B1 KR0170486 B1 KR 0170486B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gaas
- electrode
- impurities
- doped
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 230000005641 tunneling Effects 0.000 title 1
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 abstract description 16
- 230000010354 integration Effects 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 45
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
- H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
- H10D30/4738—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material having multiple donor layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10336—Aluminium gallium arsenide [AlGaAs]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 이중 피크 공명 투과 다이오드의 제조방법에 관한 것으로, 반절연성 GaAs의 반도체 기판 상에 N형 불순물이 많이 도핑된 GaAs의 버퍼층, N형 불순물이 약간 도핑된 GaAs의 제1간격층, 불순물이 도핑되지 않은 AlGaAs의 제1장벽층, 불순물이 도핑되지 않은 GaAs의 우물층, 불순물이 도핑되지 않은 AlGaAs의 제2장벽층, N형 불순물이 약간 도핑된 GaAs의 제2간격층, N형 불순물이 많이 도핑된 GaAs의 접촉을 순차적으로 결정 성장하는 공정과, 상기 버퍼층이 노출되도록 상기 접촉층 부터 버퍼층 까지 소정 부분을 건식 식각하여 메사 형태를 형성하는 공정과, 상기 버퍼층의 노출된 부분의 상부와 상기 접촉층 상부의 일측에 각각 제1 및 제2전극을 형성하는 공정과, 상술한 구조의 전 표면에 절연막을 증착한 후 메사 상부의 제2전극 및 접촉층과 메사 하부의 제1전극을 노출시키는 공정과, 상기 제2전극과 설연막을 마스크로 하여 상기 접촉층의 노출된 부분을 식각하고 상기 제1 및 제2전극 상에 도전성 금속을 증착하여 본딩 패드를 형성하는 공정을 구비한다. 따라서, 메사위에 형성된전극의 면적을 메사보다 작게하고전극이 형성되지 않는 접촉층을 부분적으로 식각하므로서 전압 강하의 차를 유도하여 전극이 형성된 영역과 형성되지 않은 영역의 이중 장벽 양자 우물 구조의 공명 투과 조건을 다르게 하여 간단하게 두개의 피크를 도출할 수 있어 고집적을 이룰 수 있다.The present invention relates to a method for manufacturing a double peak resonance transmission diode, wherein a buffer layer of GaAs heavily doped with N-type impurities, a first gap layer of GaAs slightly doped with N-type impurities, and impurities are formed on a semi-insulating GaAs semiconductor substrate. The first barrier layer of undoped AlGaAs, the well layer of GaAs undoped with impurities, the second barrier layer of AlGaAs undoped with impurities, the second gap layer of GaAs slightly doped with N-type impurities, Crystally growing a contact of heavily doped GaAs, dry etching a predetermined portion from the contact layer to the buffer layer to expose the buffer layer, and forming a mesa form, and an upper portion of the exposed portion of the buffer layer and the Forming a first electrode and a second electrode on one side of the upper contact layer, and depositing an insulating film on the entire surface of the above-described structure; Exposing a pole; and etching the exposed portion of the contact layer using the second electrode and the snow lead layer as a mask and depositing a conductive metal on the first and second electrodes to form a bonding pad. . Therefore, the area of the electrode formed on the mesa is smaller than that of the mesa, and the portion of the contact layer where the electrode is not formed is partially etched to induce a difference in voltage, thereby resonating the double barrier quantum well structure between the region where the electrode is formed and the region that is not formed By varying the conditions, two peaks can be derived simply, resulting in high integration.
Description
제1도는 이중장벽양자우물구조를 이용한 공명투과다이오드의 일반적인 전류-전압 특성.1 is a general current-voltage characteristic of a resonance transmitting diode using a double barrier quantum well structure.
제2도의 (a)는 공명투과다이오드를 이용하여 도출된 이중피크를 갖는 전류-전압 특성이며, (b) 에서 (d)는 기존의 이중피크 도출 방법.(A) of FIG. 2 is a current-voltage characteristic with a double peak derived using a resonance transmissive diode, and (b) to (d) shows a conventional double peak derivation method.
제3도(a)에서 (e)는 본 발명에 의한 이중피크공명투과다이오드 제작방법.Figure 3 (a) to (e) is a double peak resonance transparent diode manufacturing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 버퍼층1 semiconductor substrate 2 buffer layer
3,7 : 제1 및 제2간격층 4,6 : 제1 및 제2장벽층3,7: first and second gap layer 4,6: first and second barrier layer
5 : 양자우물 8 : 접촉층5: quantum well 8: contact layer
9 : 메사 10,11 : 제1 및 제2전극9 mesa 10,11 first and second electrode
12 : 절연막 13 : 본딩 패드12 insulating film 13 bonding pad
본 발명은 이중 피크 공명 투과 다이오드의 제조방법에 관한 것으로서, 특히, 이중 장벽 양자 우물 구조를 이용하여 메사의 면적 보다 적극을 작게 형성하고 접촉층을 부분적으로 식각하므로서 접촉층 및간격층에서의 전압 강하 차에 의해 이중 피크를 도출하는 이중 피크 공명 투과 다이오드의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a double peak resonance transmissive diode. In particular, a voltage drop in a contact layer and an interlayer is reduced by forming an active portion smaller than that of a mesa using a double barrier quantum well structure and partially etching the contact layer. A method for manufacturing a double peak resonance transmission diode that derives a double peak by difference.
공명 투과 현상을 이용한 다이오드나 트랜지스터는 제1 도에서 보여주듯이 인가하는 전압이 증가하여도 소자에 흐르는 전류가 감소하는 부미분저항(negative differential resistance)특성이 있어 임의의 부하선에 대하여 두 개의 안정된 성질을 갖는 쌍안정 특성이 있다. 상기 쌍안정 특성은 메모리소자나 논리회로 고주파 진동소자로 응용되어지며, 이러한 연구는 이미 세계적으로 많이 수행되어 왔다. 제2도(a)에서와 같이 하나의 부하선에 대하여 3개 혹은 그 이상의 안정된 상태를 얻게 되면 광 논리소자 및 다중 논리소자로 응용시 고집적이 가능하게 된다. 따라서, 다중 피크 도출을 위해 이중 장벽 양자 우물 구조의 공명 투과 다이오드에서 제2도(b)와 같이 이중 장벽 양자 우물 구조를 두번 수직으로 성장하는 방법과, 제2도(c)와 같이 두 개의 공명 투과 다이오드를 직릴 연결하는 방법과, 그리고, 제2도(d)와 같이 두 개의 공명 투과 다이오드를 병렬 연결하여 두개의 공명 투과 다이오드의 각각에 걸리는 전압을 조절하는 방법 등으로 두 개의 피크를 도출해내는 방법들이 있다.As shown in FIG. 1, a diode or a transistor using a resonance transmission phenomenon has a characteristic of negative differential resistance in which the current flowing through the device decreases even when an applied voltage is increased, thereby providing two stable properties for an arbitrary load line. It has a bistable characteristic with. The bistable characteristic is applied to a memory device or a logic circuit high frequency vibration device, and this research has already been performed in many parts of the world. As shown in FIG. 2A, when three or more stable states are obtained for one load line, high integration is possible when applied to optical logic devices and multiple logic devices. Thus, in a double-barrier quantum well structure resonant transmission diode, a double-barrier quantum well structure is vertically grown twice as shown in FIG. 2 (b), and two resonances as shown in FIG. 2 (c). Two peaks can be derived by connecting the transmission diodes in a straight line, and controlling the voltage applied to each of the two resonance transmission diodes by connecting two resonance transmission diodes in parallel as shown in FIG. There are ways.
그러나, 이중 장벽 양자 우물 구조를 수직으로 성장하는 방법은 에피 성장이 어려우며, 두 개의 공명 투과 다이오드를 직렬로 연결하거나 병렬로 연결하는 방법은 공정이 복잡하고 기판 상에 두 개 이상의 소자가 평면으로 연결되어야 하므로 집적도를 향상시키기 어려운 문제점이 있었다.However, the method of vertically growing a double barrier quantum well structure is difficult to grow epitaxially, and the method of connecting two resonance transmissive diodes in series or in parallel is complicated, and two or more devices on a substrate are connected in a plane. There was a problem that it should be difficult to improve the density.
따라서, 본 발명의 목적은 공명 투과 다이오드의 수직구조인 이중 장벽 양자 우물 구조를 이용하여 두 개의 피크를 도출해 냄으로서 고집적을 이룰 수 있으며 제조 공정이 간단한 이중 피크 공명 투과 다이오드를 제공함에 있다.Accordingly, an object of the present invention is to provide a double peak resonance transmission diode which can achieve high integration by deriving two peaks by using a double barrier quantum well structure which is a vertical structure of a resonance transmission diode.
상기 목적을 달성하기 위한 본 발명에 따른 이중 피크 공명투과 다이오드의 제조방법은 반절연성 GaAs의 반도체 기판 상에 N형 불순물이 많이 도핑된 GaAs의 버퍼층, N형 불순물이 약간 도핑된 GaAs의 제1간격층, 불순물이 도핑되지 않은 AlGaAs의 제1장벽층, 불순물이 도핑되지 않은 GaAs의 우물층, 불순물이 도핑되지 않은 AlGaAs의 제2장벽층, N형 불순물이 약간 도핑된 GaAs의 제2간격층, N형 불순물이 많이 도핑된 GaAs의 접촉층을 순차적으로 결정 성장하는 공정과, 상기 버퍼층이 노출되도록 상기 접촉층부터 버퍼층까지 소정 부분을 식각하여 메사 형태를 형성하는 공정과, 상기 버퍼층의 노출된 부분의 상부와 상기 접촉층 상부의 일측에 각각 제1 및 제2전극을 형성하는 공성과, 상술한 구조의 전 표면에 절연막을 증착한 후 메사 상부의 제2전극 및 접촉층과 메사하부의 제1전극을 노출시키는 공정과, 상기 제2전극과 절연막을 마스크로 하여 상기 접촉층의 노출된 부분을 직각하고 상기 제1 및 제2전극 상에 금속을 증착하여 본딩 패드를 형성하는 공정을 구비한다.In order to achieve the above object, a method of manufacturing a double peak resonance transmissive diode according to the present invention includes a buffer layer of GaAs heavily doped with N-type impurities and a first interval of GaAs slightly doped with N-type impurities on a semi-insulating GaAs semiconductor substrate. Layer, a first barrier layer of AlGaAs without doping impurities, a well layer of GaAs without doping impurities, a second barrier layer of AlGaAs without doping impurities, a second gap layer of GaAs slightly doped with N-type impurities, Crystally growing a contact layer of GaAs heavily doped with N-type impurities, etching a predetermined portion from the contact layer to the buffer layer to expose the buffer layer, and forming a mesa form, and an exposed portion of the buffer layer The first electrode and the second electrode on the upper side of the contact layer and the upper side of the contact layer, respectively, and after depositing an insulating film on the entire surface of the structure described above, the second electrode and the contact layer and the Exposing the first electrode of the lower part, and forming a bonding pad by depositing metal on the first and second electrodes at right angles to the exposed portions of the contact layer using the second electrode and the insulating layer as a mask. It is provided.
이하 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도(a) 내지 (e)는 본 발명에 따른 이중 피크 공명 투과 다이오드의 제조 공정도이다.3 (a) to (e) are process charts for manufacturing a double peak resonance transmission diode according to the present invention.
제3도(a)를 참조하면, 반절연성 GaAs 반도체 기판(1) 상에 N형 불순물이 많이 도핑된 GaAs 버퍼층(2), N형 불순물이 약간 도핑된 GaAs 제1간격층(3), 불순물이 도핑되지 않은 AlGaAs 제1장벽층(4), 불순물이 도핑되지 않은 GaAs 우물층(5), 불순물이 도핑되지 않은 AlGaAs 제2장벽층(6), N형 불순물이 약간 도핑된 GaAs 제2간격층(7), N형 불순물이 많이 도핑된 GaAs 접촉층(8)을 순차적으로 결정 성장하여 형성한다. 상기에서, 결정 성장층들은 MBE 또는 MOCVD 등의 방법으로 형성된다. 또한, 접촉층(8)은 불순물을 1× 1018∼5×1018cm-3정도의 고농도로 도핑하여 전기 전도도를 크게 하며 이중 장벽 양자 우물 구조를 이루는 제2장벽층(6)의 상부에 형성된 제2간격층(7)은 1× 1017∼5×1017cm-3정도로 도핑하여 100∼150nm 정도로 형성한다.Referring to FIG. 3A, a GaAs buffer layer 2 heavily doped with N-type impurities, a GaAs first gap layer 3 slightly doped with N-type impurities, and impurities are formed on the semi-insulating GaAs semiconductor substrate 1. The undoped AlGaAs first barrier layer 4, the impurity doped GaAs well layer 5, the impurity doped AlGaAs second barrier layer 6, and the N-type impurity GaAs second gap A layer 7 and a GaAs contact layer 8 heavily doped with N-type impurities are sequentially formed by crystal growth. In the above, the crystal growth layers are formed by a method such as MBE or MOCVD. In addition, the contact layer 8 is doped with impurities at a high concentration of about 1 × 10 18 to 5 × 10 18 cm -3 to increase the electrical conductivity and to the upper part of the second barrier layer 6 forming a double barrier quantum well structure. The formed second gap layer 7 is doped with about 1 × 10 17 to 5 × 10 17 cm −3 to form about 100 to 150 nm.
제3도(b)를 참조하면, 상술한 구조를 상기 버퍼층(2)이 노출 되도록 식각 방법에 의해 식각하여 메사(mesa:9) 형태를 형성한다. 그리고, 상기 버퍼층(2)의 노출된 부분의 상부와 접촉층(8) 상부의 일측에 각각 제1 및 제2전극(10)(11)을 형성한다. 상기에서 접촉층(8) 상부의 일측에 형성된 제2전극(11)은 메사(9)의 한쪽 끝에 부분적으로 형성되도록 하며, 제1 및 제2전극(10)(11)이 오음 접촉을 이루도록 고속 열처리 방법으로 열처리한다. 상기에서, 메사(9)의 상부와 제2전극(11)은 면적의 차가 크면 제2전극(11)이 형성되지 않은 영역의 공명 투과에 의한 전류피크가 제2전극(11)이 형성된 영역의 비공명 투과 전류 보다 작게 되어 피크가 나타나지 않게 되며, 면적 차가 작으면 첫 번째 밸리점 근처에서 공명 투과의 조건을 만족하게 되어 첫 번째 밸리만 증가시키게 된다. 따라서, 메사(9)의 상부와 제2전극(11)의 면적 비는 1.5∼3:1 정도가 적합하다.Referring to FIG. 3B, the above-described structure is etched by an etching method so that the buffer layer 2 is exposed to form a mesa 9. The first and second electrodes 10 and 11 are formed on one side of the exposed portion of the buffer layer 2 and one side of the contact layer 8, respectively. In the above, the second electrode 11 formed on one side of the upper contact layer 8 is partially formed at one end of the mesa 9, and the first and second electrodes 10 and 11 are formed at high speed so as to make ohmic contact. Heat treatment by heat treatment method. In the above, when the difference in the area between the upper portion of the mesa 9 and the second electrode 11 is large, the current peak due to resonance transmission of the region where the second electrode 11 is not formed is obtained in the region where the second electrode 11 is formed. It is smaller than the non-resonant transmission current so that no peak appears. When the area difference is small, the condition of the resonance transmission is satisfied near the first valley point, thereby increasing only the first valley. Therefore, the ratio of the area of the upper portion of the mesa 9 and the second electrode 11 is preferably about 1.5 to 3: 1.
제3도(c)를 참조하면, 상술한 구조의 전 표면에 실리콘산화막 또는 실리콘 질화막 등의 절연막(12)을 증착한 후 메사(9) 상부에 형성된 제2전극(11) 및 접촉층(8)과 메사(9) 하부의 제1전극(10)을 노출시킨다.Referring to FIG. 3 (c), after depositing an insulating film 12 such as a silicon oxide film or a silicon nitride film on the entire surface of the structure described above, the second electrode 11 and the contact layer 8 formed on the mesa 9 are formed. ) And the first electrode 10 under the mesa 9 are exposed.
제3도(d)를 참조하면, 상기 제1 및 제2전극(10)(11)과 절연막(12)을 마스크로 하여 상기 접촉층(8)의 노출된 부분을 식각한다. 그리고, 제1 및 제2전극(10)(11) 상에 금속을 증착하여 본딩패드 (13)를 형성한다.Referring to FIG. 3D, exposed portions of the contact layer 8 are etched using the first and second electrodes 10 and 11 and the insulating layer 12 as masks. Then, metal is deposited on the first and second electrodes 10 and 11 to form a bonding pad 13.
상술한 바와 같이 본 발명은 다수의 결정 성장층들을 결정 성장하고 메사 형태로 식각한 후 상기 메사의 하부와 상부에 제1 및 제2전극을 형성할 때 상기 제2전극을 메사 상부의 면적에 비하여 작게 형성하고, 상기 제2전극과 절연막을 마스크로 하여 노출된 접촉층을 부분적으로 식각하면 제2전극이 형성되지 않은 영역의 이중 장벽 양자 우물구조에 인가되는 전압이 차이가 나게 되어 제2전극이 형성된 영역과 형성되지 않은 영역이 서로 다른 인가 전압하에서 공명 투과 조건이 만족되므로 두 개의 공명 투과 피크가 나타나게 된다. 따라서, 본 발명은 전극의 면적을 작게하고 전극이 형성되지 않은 접촉층을 부분적으로 식각하므로서 전압 강하의 차를 유도하여 전극이 형성된 영역과 형성되지 않은 영역의 이중 장벽 양자 우물 구조의 공명 투과 조건을 다르게 하여 간단하게 두 개의 피크를 도출할 수 있어 고집적을 이룰 수 있는 잇점이 있다.As described above, according to the present invention, when the first and second electrodes are formed on the bottom and top of the mesa after crystal growth of a plurality of crystal growth layers and etching in a mesa form, the second electrode is larger than the area of the top of the mesa. Forming a small layer and partially etching the exposed contact layer using the second electrode and the insulating layer as a mask causes a difference in voltage applied to the double barrier quantum well structure in the region where the second electrode is not formed. Since the resonance transmission conditions are satisfied between the formed region and the unformed region under different applied voltages, two resonance transmission peaks appear. Accordingly, the present invention reduces the area of the electrode and partially etches the contact layer where the electrode is not formed, thereby inducing a difference in voltage, thereby reducing the resonance transmission condition of the double barrier quantum well structure between the region where the electrode is formed and the region where the electrode is not formed. Alternatively, two peaks can be simply derived to achieve high integration.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050516A KR0170486B1 (en) | 1995-12-15 | 1995-12-15 | Fabrication method of double peak resonant tunneling diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050516A KR0170486B1 (en) | 1995-12-15 | 1995-12-15 | Fabrication method of double peak resonant tunneling diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970054537A KR970054537A (en) | 1997-07-31 |
| KR0170486B1 true KR0170486B1 (en) | 1999-02-01 |
Family
ID=19440479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050516A KR0170486B1 (en) | 1995-12-15 | 1995-12-15 | Fabrication method of double peak resonant tunneling diode |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0170486B1 (en) |
-
1995
- 1995-12-15 KR KR1019950050516A patent/KR0170486B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970054537A (en) | 1997-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5244834A (en) | Semiconductor device | |
| US5633516A (en) | Lattice-mismatched crystal structures and semiconductor device using the same | |
| US6242762B1 (en) | Semiconductor device with a tunnel diode and method of manufacturing same | |
| KR101922107B1 (en) | Semiconductor device and method of manufacturing the same | |
| US3961996A (en) | Process of producing semiconductor laser device | |
| JPH01146390A (en) | Semiconductor device | |
| US5665612A (en) | Method for fabricating a planar buried heterostructure laser diode | |
| JP5205729B2 (en) | Semiconductor laser device and manufacturing method thereof | |
| JPS62160785A (en) | Monolithic semiconductor structure and its manufacturing method | |
| KR0170486B1 (en) | Fabrication method of double peak resonant tunneling diode | |
| JPH01198088A (en) | Semiconductor laser and manufacture thereof | |
| JPH0740570B2 (en) | Resonance tunneling device | |
| JP2583793B2 (en) | Semiconductor substrate | |
| US6081000A (en) | AlAs oxide insulating layer between a conductive III-V substrate and an optoelectronic semiconductor device and method of manufacturing thereof | |
| JPH01212483A (en) | Semiconductor device | |
| KR19980030477A (en) | How to make quantum thin line laser diode | |
| KR960002646B1 (en) | The compound semiconductor device and the manufacturing method thereof | |
| JPS61216468A (en) | semiconductor equipment | |
| JPS61189663A (en) | Semiconductor integrated circuit and its manufacturing method | |
| JPS63157467A (en) | Hetero junction bipolar transistor | |
| JPH10510102A (en) | Ridge laser in channel | |
| JPH08264876A (en) | Light emitting element | |
| KR960002991A (en) | Compound Semiconductor Laser Diode and Manufacturing Method Thereof | |
| JPH01143383A (en) | Optoelectronic integrated circuit and manufacture thereof | |
| JPS6065577A (en) | Extremely short gate, field effect transistor having horizontal structure and method of producing same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951215 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19951215 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19980831 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19981015 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19981015 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20010927 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20020930 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20031001 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20041001 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20051011 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20061002 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20070919 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20070919 Start annual number: 10 End annual number: 10 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20090910 |