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JPS60124069U - Printed board - Google Patents

Printed board

Info

Publication number
JPS60124069U
JPS60124069U JP1177884U JP1177884U JPS60124069U JP S60124069 U JPS60124069 U JP S60124069U JP 1177884 U JP1177884 U JP 1177884U JP 1177884 U JP1177884 U JP 1177884U JP S60124069 U JPS60124069 U JP S60124069U
Authority
JP
Japan
Prior art keywords
printed board
circuit board
printed circuit
land
flat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1177884U
Other languages
Japanese (ja)
Inventor
岩崎　勝四郎
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1177884U priority Critical patent/JPS60124069U/en
Publication of JPS60124069U publication Critical patent/JPS60124069U/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案に係るプリント基板にＦＩＣを取付けた
場合の実装平面図、第２図は第１図に於けるプリント基
板の要部平面図である。 ３・・・フラットパック型半導体集積回路（ＦＩＣ）、
７・・・リード線、１３・・・半田、１１・・・ランド
部分、２１・・・切削部分、１・・・プリント基板。FIG. 1 is a mounting plan view when an FIC is attached to a printed circuit board according to the present invention, and FIG. 2 is a plan view of essential parts of the printed circuit board in FIG. 1. 3... Flat pack semiconductor integrated circuit (FIC),
7... Lead wire, 13... Solder, 11... Land portion, 21... Cutting portion, 1... Printed circuit board.

Claims (1)

【実用新案登録請求の範囲】 フラットパック型半導体集積回路のフラット状のリード
線を半田付けにより固定する導電箔のランド部分に於い
て、 前記リード線が前記ランド部分に載置される位置の前記
ランド部分に切削部分を具備したことを特徴とするプリ
ント基板。[Claims for Utility Model Registration] In a land portion of a conductive foil for fixing a flat lead wire of a flat pack type semiconductor integrated circuit by soldering, A printed circuit board characterized by having a cutting part in the land part.
JP1177884U 1984-01-31 1984-01-31 Printed board Pending JPS60124069U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1177884U JPS60124069U (en) 1984-01-31 1984-01-31 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1177884U JPS60124069U (en) 1984-01-31 1984-01-31 Printed board

Publications (1)

Publication Number Publication Date
JPS60124069U true JPS60124069U (en) 1985-08-21

Family

ID=30494215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1177884U Pending JPS60124069U (en) 1984-01-31 1984-01-31 Printed board

Country Status (1)

Country Link
JP (1) JPS60124069U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04119962U (en) * 1991-04-10 1992-10-27 オムロン株式会社 Terminal pin mounting structure on circuit board
WO2013186927A1 (en) * 2012-06-15 2013-12-19 株式会社日立製作所 Printed board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04119962U (en) * 1991-04-10 1992-10-27 オムロン株式会社 Terminal pin mounting structure on circuit board
WO2013186927A1 (en) * 2012-06-15 2013-12-19 株式会社日立製作所 Printed board

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