JPS60109358U - Block board connection structure - Google Patents
Block board connection structureInfo
- Publication number
- JPS60109358U JPS60109358U JP19913883U JP19913883U JPS60109358U JP S60109358 U JPS60109358 U JP S60109358U JP 19913883 U JP19913883 U JP 19913883U JP 19913883 U JP19913883 U JP 19913883U JP S60109358 U JPS60109358 U JP S60109358U
- Authority
- JP
- Japan
- Prior art keywords
- block board
- connection structure
- board
- board connection
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
一第１図〜第３図は従来例を示し、第１図はブロック基
板の平面図、第２図は第１図に示したブロック基板をデ
ィップ半田するために接続ピンをプリント基板に差込ん
で立設した状態を示す斜視図、第３図は第２図に示すプ
リント基板の要部平面図である。第４図は他の従来例の
ブロック基板の平面図である。第５図及び第６図は本考
案の実施例を示し、第５図は円筒形をしたブロック基板
の斜視図、第６図は第５図のブロック基板をプリント基
板にリフロー半田した状態を示す斜視図である。、
１．６・・・ブロック基板、２・・・チップ部品、３゜
７・・・導体パターン、５・・・プリント基板。- Figures 1 to 3 show conventional examples, Figure 1 is a plan view of a block board, and Figure 2 is a connection pin inserted into a printed circuit board for dip soldering of the block board shown in Figure 1. FIG. 3 is a perspective view showing the printed circuit board in an upright state; FIG. 3 is a plan view of the main parts of the printed circuit board shown in FIG. 2; FIG. 4 is a plan view of another conventional block substrate. Figures 5 and 6 show an embodiment of the present invention, Figure 5 is a perspective view of a cylindrical block board, and Figure 6 shows the block board of Figure 5 reflow soldered to a printed circuit board. FIG. , 1.6...Block board, 2...Chip component, 3゜7...Conductor pattern, 5...Printed board.
Claims (1)
ロック基板と、該ブロック基板を取付け゛ るプリ
ント基板とより成り、前記プリント基板上に前記円筒状
のブロック基板を半田接続したことを特徴とするブロッ
ク基板の接続構造。It is characterized by comprising a block board formed by bending a flexible thin insulating plate into a cylindrical shape, and a printed circuit board to which the block board is attached, and the cylindrical block board is connected to the printed board by soldering. Block board connection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19913883U JPS60109358U (en) | 1983-12-28 | 1983-12-28 | Block board connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19913883U JPS60109358U (en) | 1983-12-28 | 1983-12-28 | Block board connection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60109358U true JPS60109358U (en) | 1985-07-25 |
Family
ID=30758777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19913883U Pending JPS60109358U (en) | 1983-12-28 | 1983-12-28 | Block board connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109358U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015094259A1 (en) | 2013-12-19 | 2015-06-25 | Intel Corporation | Flexibly-wrapped integrated circuit die |
-
1983
- 1983-12-28 JP JP19913883U patent/JPS60109358U/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015094259A1 (en) | 2013-12-19 | 2015-06-25 | Intel Corporation | Flexibly-wrapped integrated circuit die |
| CN106030781A (en) * | 2013-12-19 | 2016-10-12 | 英特尔公司 | Soft wrapped integrated circuit die |
| EP3084824A1 (en) * | 2013-12-19 | 2016-10-26 | Intel Corporation | Flexibly-wrapped integrated circuit die |
| JP2016537814A (en) * | 2013-12-19 | 2016-12-01 | インテル・コーポレーション | Integrated circuit die device, integrated circuit die device encased with flexibility, and method of mounting an integrated circuit die encased with flexibility on a substrate |
| EP3084824A4 (en) * | 2013-12-19 | 2017-08-16 | Intel Corporation | Flexibly-wrapped integrated circuit die |
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