JPS5979536A - Resin-sealed type semiconductor device - Google Patents
Resin-sealed type semiconductor deviceInfo
- Publication number
- JPS5979536A JPS5979536A JP57190202A JP19020282A JPS5979536A JP S5979536 A JPS5979536 A JP S5979536A JP 57190202 A JP57190202 A JP 57190202A JP 19020282 A JP19020282 A JP 19020282A JP S5979536 A JPS5979536 A JP S5979536A
- Authority
- JP
- Japan
- Prior art keywords
- island
- resin
- semiconductor device
- leads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体素子を金属板の小片（アイランドと称
す）に搭載し、樹脂封止した樹脂封止型の半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device in which a semiconductor element is mounted on a small piece of a metal plate (referred to as an island) and sealed with a resin.
従来の樹脂封止型半導体装置は、集積回路素子などの半
導体素子を搭載するアイランドと、アイランドに搭載し
た半導体素子の電極からの電気接続をとるだめの多数の
引出しリードとは、プレス加工などにより一枚の金属板
から一体に形成されておった。したがって、アイランド
の周囲に多数の引き出しリードの先端部（ステッチと称
す）が集るような配置となって、アイランドの中央部に
搭載した半導体素子と各リードのステッチとの距離を短
くして短いボンディング線でこの間を接続しようとすれ
ば、当然アイランドの面積も小さくせざるを得す、この
アイランドを通して封止樹脂に放熱せられるべき放熱効
果も充分には期待できず、このようなアイランドに消＊
電力の大きい集積回路素子を搭載することはできなかっ
た。In a conventional resin-sealed semiconductor device, an island on which a semiconductor element such as an integrated circuit element is mounted, and a large number of lead-out leads for making electrical connections from the electrodes of the semiconductor element mounted on the island are separated by a process such as press processing. It was made of one piece of metal. Therefore, the tips of many lead leads (referred to as stitches) are arranged around the island, shortening the distance between the semiconductor element mounted in the center of the island and the stitches of each lead. If you try to connect this area with a bonding wire, you will naturally have to reduce the area of the island, and the heat dissipation effect that should be radiated to the sealing resin through this island cannot be expected to be sufficient. *
It was not possible to mount integrated circuit elements with large amounts of power.
本発明の目的は、半導体素子を搭載したアイランドから
の放熱特性を改善して消費電力の大きい半導体素子を備
えしめた樹脂封止型の半導体装置を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-sealed semiconductor device equipped with a semiconductor element that consumes a large amount of power by improving heat dissipation characteristics from an island on which a semiconductor element is mounted.
本発明の樹脂封止型半導体装置は、半導体素子を搭載し
たアイランドと、このアイランドと別個に製造され、先
端部が前記半導体素子の周囲に配置された多数のリード
と、前記半導体素子およびリード先端部を共に封止した
封止樹脂とを含む構成を有する。The resin-sealed semiconductor device of the present invention includes an island on which a semiconductor element is mounted, a large number of leads manufactured separately from the island and whose tips are arranged around the semiconductor element, and the semiconductor element and the tips of the leads. It has a structure including a sealing resin that seals both parts.
つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.
第１図（ａ） 、 （ｂｌ 、 （ｃｌはそれぞれ、本
発明の一実施例のｔＭ １４Ｊｉ而図、縦断面図、封止
樹脂を透視した平面図である。これらの図に２いて、半
導体素子、例えシＪｊ集積回路素子３を搭載したアイラ
ンド４と、集積回路素子３の周囲に先端部が集るように
配置された多数のリード２とは別々に製作されているも
のであシ、アイランド４に搭載した集積回路素子３およ
びリード２のステッチならびに集積回路素子３の′市、
極とり一層２のステッチとの間を接続したポンディフグ
線５は、封止樹脂１により共に封止されている３、）
しかして、本発明では、アイランド４とリード２どは別
個に作られているので、従来のような一体製造のものの
ように形状に制限を受けることなく、アイランド４の上
方にリード２が位置されるようにもアイランドの形を大
きくでき、よって、集積回路素子３からアイランド４に
伝導し、さらに封止樹脂１に逃げる集積回路素子の発生
熱の放散の効率を大きく改善し、消費電力の大きい集積
回路素子でも、大きな放熱効果により、温度上Ｕ−が押
さえられて叶カ一杯の働らきをさせることができる。寸
だ、従来のアイランドとリードとの一体購成の場合、リ
ード２０強度の点で材質は制限されたが、アイランド４
とリード２とを別々に作ることにより、アイランド４の
材質をリード２と異なった熱伝導の高い材料とすること
により、単に形を太きくしたよりも一層の放熱効果の上
昇が得られる。FIG. 1(a), (bl, and (cl) are respectively a tM 14J diagram, a vertical sectional view, and a plan view seen through the sealing resin of an embodiment of the present invention. An island 4 on which an element, for example an integrated circuit element 3 is mounted, and a large number of leads 2 arranged so that their tips are gathered around the integrated circuit element 3 are manufactured separately. stitching of the integrated circuit element 3 and the lead 2 mounted on the island 4, and the stitching of the integrated circuit element 3;
The Pondifugu wire 5 connected between the poles and the stitches of the first layer 2 is sealed together with the sealing resin 1.3) Therefore, in the present invention, the island 4 and the lead 2 are made separately. Therefore, the shape of the island can be enlarged so that the leads 2 are positioned above the island 4 without being limited in shape as in the case of conventional integrated circuit manufacturing. This greatly improves the efficiency of dissipating the heat generated by the integrated circuit element, which is conducted to 4 and further escapes to the sealing resin 1. Even in integrated circuit elements with large power consumption, the large heat dissipation effect suppresses U- in terms of temperature, making it possible to achieve It can be made to do a lot of work. In the case of conventional purchasing of an island and a lead, the material was limited by the strength of the lead 20, but the island 4
By making the island 4 and the lead 2 separately, and by making the island 4 a material with high thermal conductivity different from that of the lead 2, a further increase in heat dissipation effect can be obtained than simply making the shape thicker.
このように本発明によれは、アイランド４とリード２と
を別個に製造することにより、外形を変えずにアイラン
ド４のみを太きくシ、さらに利料の制限からも免れて、
熱伝導の高い材料がアイランドを作り、大消費電力の樹
脂封止型半導体装置を実現可能にしている。In this way, according to the present invention, by manufacturing the island 4 and the lead 2 separately, only the island 4 can be made thicker without changing the external shape, and furthermore, it is possible to avoid the restrictions on the interest rate.
Materials with high thermal conductivity create islands, making it possible to create resin-sealed semiconductor devices with high power consumption.
！！１図ｆａ） 、 （ｂｌ 、 （ｃ）はそれぞれ本
発明の一実施例の（１へ断面図、縦断面図、封止樹脂を
透視した平面図である。
１・・・・・・封止鉗脂、２・・・・・・リード、３・
・・・・・集積回路素子、４・・・・・・アイランド、
５・・・・・・ポンディング綾。
躬 １ 〆! ! Figures 1 (fa), (bl) and (c) are a cross-sectional view, a longitudinal cross-sectional view, and a plan view looking through the sealing resin, respectively, of an embodiment of the present invention.1...Sealing Ribbon, 2...Reed, 3.
...Integrated circuit element, 4...Island,
5...Pounding Aya. 1 〆
Claims (1)
半導体素子の周囲に集るように多数のリードを配置し、
樹脂で封止した樹脂封止型半導体装Ｒ７において、前記
アイランドとリードとは別個に製造されていることを特
徴とする樹脂封止型半導体装１ｄ。 （２） 上記アイランドは上記リードより熱抵抗の小
さい材ｔ１を用いて別個に製造されていることを特徴と
する特許請求の範囲第１項に記載の樹脂制止型半導体装
置。[Claims] (11 semiconductor elements are mounted on an island, and a large number of leads are arranged so that their tips are gathered around the semiconductor elements,
A resin-sealed semiconductor device 1d characterized in that in a resin-sealed semiconductor device R7, the island and the leads are manufactured separately. (2) The resin-sealed semiconductor device according to claim 1, wherein the island is manufactured separately using a material t1 having a lower thermal resistance than the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57190202A JPS5979536A (en) | 1982-10-29 | 1982-10-29 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57190202A JPS5979536A (en) | 1982-10-29 | 1982-10-29 | Resin-sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5979536A true JPS5979536A (en) | 1984-05-08 |
Family
ID=16254150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57190202A Pending JPS5979536A (en) | 1982-10-29 | 1982-10-29 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5979536A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62269325A (en) * | 1986-05-16 | 1987-11-21 | Mitsubishi Electric Corp | Semiconductor device |
| WO1992004730A1 (en) * | 1990-09-10 | 1992-03-19 | Fujitsu Limited | Semiconductor device and its manufacturing process |
-
1982
- 1982-10-29 JP JP57190202A patent/JPS5979536A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62269325A (en) * | 1986-05-16 | 1987-11-21 | Mitsubishi Electric Corp | Semiconductor device |
| WO1992004730A1 (en) * | 1990-09-10 | 1992-03-19 | Fujitsu Limited | Semiconductor device and its manufacturing process |
| US5440170A (en) * | 1990-09-10 | 1995-08-08 | Fujitsu Limited | Semiconductor device having a die pad with rounded edges and its manufacturing method |
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