JPS59177945A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and in particular to a high speed, low power consumption gate array LSI (Large 5ca) consisting of CMOS transistors and bipolar transistors.
The present invention relates to a semiconductor integrated circuit device suitable for LE Integration.

[Background of the invention]

Gate array LSI is a device that manufactures LSIs with desired electrical circuit operation by creating only the mask corresponding to the wiring out of the more than 10 photomasks used when manufacturing LSIs according to the product being developed. be. It is said that the concept of this master slice method has been around since the 1960s.

The configuration of a gate array LSI is shown in FIG.

The semiconductor chip 10 has a bonding pad and an input/output circuit area 14 on its outer periphery, and inside it, basic cells 11' consisting of elements such as transistors & basic cell rows 12 arranged in the X direction are repeatedly arranged with a wiring area 13 in between. The structure is arranged in parallel in the direction.

In order to obtain the desired electrical circuit operation, adjacent basic cells 1
One or several 1's are connected to form a NAND gate, flip-flop, etc. and a plurality of basic cells 11
One LSI is constructed by wiring the various logic gates formed in accordance with the logic diagram.

In the conventional CMOS gate array LSI, the basic cell 11
is composed of CMOS transistors.

The 0M08 circuit has the advantage of low power consumption, but because the transfer conductance of the MOS transistor is small, it takes time to charge and discharge when the load capacity is large, resulting in a slow speed.

In the conventional bipolar gate array LSI, the basic cell 11 is composed of a bipolar transistor, a resistor, and the like. Bipolar circuits have the advantage of not slowing down even when the load capacitance increases because the conductance of bipolar transistors is larger than that of MOS transistors. The drawback is that it consumes a lot of power because it has to be drained or drained.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a high-speed, low power consumption, highly integrated semiconductor integrated circuit device.

[Summary of the invention]

The present invention focuses on the low power consumption characteristics of the 0M08 circuit and the high drive ability characteristics of the bipolar circuit, and uses a basic cell that can configure a bipolar and CMO8 composite circuit that combines both circuits to achieve high speed and low power consumption. The present invention aims to obtain a semiconductor integrated circuit device.

[Embodiments of the invention] Hereinafter, the present invention will be explained in detail with reference to Examples.

The 21st cell pattern 1 is an enlarged version of the cell pattern of the basic cell 11. FIG. 3 conceptually shows a sectional view thereof to aid understanding. Identical parts in FIGS. 2 and 3 are designated by the same numbers. In an N well 21 provided on a P-type semiconductor substrate, a bi region 23 constituting a PMO transistor, and a collector region 24, a base region 25, and an emitter region 26 constituting an NPN bipolar transistor are formed. That is, a PMO8 transistor and an NPN bipolar transistor are configured in one N-well. This changes the potential of the collector region 24 to the power supply potential V
By using it in the circuit part to be CC, the potential of the substrate of the 2MO8) transistor (in this case, N well 21) is changed to NP.
Fixed at the collector potential of the N bipolar transistor,
This is intended to promote integration.

A collector region 27, a base region 28, and an emitter region 29 forming an NPN bipolar transistor are formed in the N well 22. This is used in a circuit portion where the potential of the collector region 27 changes. N-well 21
Since it is necessary to electrically insulate the space between the N-well 22 and the N-well 22 by a P-type region 37 lowered to the ground potential, it is necessary to provide a distance determined by the withstand voltage or the like. P-type region 37 dropped to ground potential here
Noting that this corresponds to the substrate of the NMO8) transistor, an N+ region 30 constituting the NMO8) transistor is formed between the N wells 21 and 22. Similarly NMO8)
N+ regions 31 and 32 forming transistors are formed. P+ region 33 is provided to lower the potential of P region 37 to ground potential. 35°36 x 2 MO8) transistors and NMO8) transistor gate electrodes made of polysilicon or the like serve as input sections. A bulge (generally called a dog bone) is provided at both ends of the I-H channel region 13 so that it can be contacted with the first wiring such as the first layer A L so that input can be made to the basic cell from either the upper side or the lower side of the I-H channel region 13. ing. 34 is the gate electrode of two NMO8) transistors. The output is generally a connector area 27 formed in the N well 22, but the input part 35, 36 and the output part 27 are the wiring of the second wiring such as the second layer AL running in the y direction in FIG. Same size as pitch - automatic design (Des
ign Automation +DA).

There is a first insulating film (not shown) on the poly-Si wiring constituting the gate electrodes 35, 36, 34, etc., and on this
, etc., in the longitudinal direction parallel to the basic cell row, and connect the power supply wiring and A
4 first wirings (not shown) are formed. Here, the first wiring connects within a logical block and between logical blocks. Poly S1 wiring 34 etc. or diffusion layer 23 etc. and At
When it is necessary to connect the first wiring to the first wiring, a contact hole (hereinafter simply referred to as a contact) is opened in the first insulating film.

A second insulating film (not shown) is disposed on the first wiring, and a second insulating film (not shown) of the AA is further disposed on the first insulating film so that its longitudinal direction is orthogonal to the basic cell row.
Wiring is formed. When it is necessary to connect the first wiring and the second wiring, a contact hole (hereinafter referred to as
(referred to as a through hole). There is a third insulating film on the top layer, which protects the transistors and wiring. In general gate arrays T and SI, when obtaining the desired LSI by changing the first wiring, the second wiring, and the second insulating film provided with through holes in the necessary parts to connect the two for each type. There are many. In addition, there are also examples in which the first insulating film, in which contacts are provided in areas necessary for connecting the first wiring to the poly-Si wiring and the diffusion layer, is also changed.

By using a basic cell as shown in FIG. 2, it is possible to construct a logic circuit necessary for designing an LSI.

Examples of these will be explained below.

FIG. 4 shows a two-man power NAND circuit, which is an example of a bipolar CMO8 composite circuit, which was previously filed by the present applicant (Japanese Patent Application No. 188942, No. 57-(9)).

In FIG. 4, 50 has a collector connected to the power supply terminal 40,
a first NPN bipolar transistor (hereinafter simply referred to as first NPN) whose emitter is connected to the output terminal 43;
Reference numeral 51 denotes a second NPN bipolar transistor (hereinafter simply referred to as second NPN), whose collector is connected to the output terminal 43 and whose emitter is connected to a fixed potential terminal that is at ground potential.
and 42 are two input terminals, and 44 and 45 have gates connected to different input terminals 42 and 41, respectively, and sources and drains connected in parallel between the collector and base of the first NPN 50, respectively. 1st and 2nd 2MO
8) Transistor (hereinafter simply referred to as first 2MO8, second 2M)
O8), 46 and 47 are connected in series, respectively, with each gate connected to a different input terminal 41 and 42, and each drain and each source connected in series between the collector and the pace of the second NPN 51, respectively. 2 NMO8I - transistor C hereinafter simply referred to as first NMO8 and second NMO8)
, 48 is (10) whose gate is connected to the power supply terminal 40 and whose drain and source are connected to the first O
3rd N connected to NPN500 base and emitter
A MOS transistor (hereinafter simply referred to as the third N'MO8) 49 is a fourth NMO8 transistor (hereinafter simply referred to as the fourth N'MO8) whose gate is connected to the power supply terminal 40 and whose drain and source are connected to the base and emitter of the second ONPN 510. N.M.O.
8).

Table 1 shows the logical operation of the circuit of FIG.

Table 1 First, when either input 41 or 42 is at 0# level,
Either the first or second PMO 844, 45 is turned on, and either the first or second ONMO 846, 47 (11) is turned off. Therefore the first NPN50
, the base potential of the first NPN 50 rises, the first NPN 50 turns on, and the second NPN 51 turns on the fourth NPN 8 which is in the non-saturation region.
Since the base and emitter are short-circuited through NPN 49 and turned off, the emitter current of the first NPN 50 charges the load and the output 43 rises to the "1#" level.

When both inputs 41 and 42 are at 0'' level, the first and second
Both PMOs 844 and 45 are turned on, and the first and first
Both NMOs 846 and 47 are turned off. Therefore, the operation is the same as above, and the output is 43/1#.

On the other hand, when both inputs 41 and 42 are at the "1" level, the first
, both second PMOs 844 and 45 are turned off, and the first
, both of the second NMOs 846 and 47 are turned on. Therefore, the first NPN 50 is short-circuited between the base and emitter via the third NMO 848 in the non-saturation region and turned off, and the first NPN 50 is turned off between the collector and base of the second NPN 51.
Second NMO846.

47, the second NPN 51 (12
) is supplied with current from the output 43, and the second ONP
N51 is turned on, and the output 43 rises to the "0" level.

The fourth NMO 848, 49 may be a simple resistance element.

FIG. 5 shows this two-man powered NAND circuit constructed using the basic cell shown in FIG. 2. In FIG. 5, the dotted lines indicate contacts, the broken lines indicate the first wiring 2, the through holes, and the dashed dotted lines indicate the second wiring. Parts that are the same as those in FIG. 2 are designated by the same numbers. In order to correspond with Figure 4, element numbers are given on the gate electrodes, etc.

The first wiring 52, which becomes the VCC power supply line, is connected to the source of the second PMO 845 through the contact 53, to the source of the first PMO 844 through the contact 54, to the collector of the first ONPN 50 through the contact 55, and to the collector of the first ONPN 50 through the contact 56. 3. 4th NMO848, 49
are connected to gate electrodes 34, respectively. The first and second wirings 57 and contacts 59, 58, and 60
The drain of PM(13) 0844.45, the base of the first ONPN 50, and the drain of the third NMO 848 are connected to each other. 1st wiring 61.62 contact 63°64.65
, 66 and 67, the emitter of the first NPN 56, the source of the third NMO 848, the drain of the first NMO 846, and the collector of the second NPN 51 are connected, respectively. Further, the emitter of the first NPN 50 and the collector of the second NPN 51 are connected through the second wiring 68 and through holes 69 and 70. This means that if this second wiring 68 is not present, the emitter of the first NPN 50 and the second NP
This is provided to prevent the sheet resistance of the drain of the first NMO 846 from entering between the collector of N51 and reducing the speed. - Also, this second wiring 68 is on a lattice of second wirings running in the y direction, minimizing interference with the first wiring 71, contacts 72 . ．． 73.7
4 by the source of the second NMOS 47, the fourth ONMO
The drain of 849 and the base of second NPN 51 are connected to each other.

The first wiring 75, which becomes the ground potential line, is connected to the contour (14
) source of the fourth NMO 849 by cts 76, 77;
Connected to the emitter of the second NPN 51.

Contact 78 connects P substrate 37 to ground potential.

Regarding the thickness of the wiring such as A and L, the first wiring 52.75 serving as the power supply line is thick, and the first wiring 61.62 and the second wiring 6 through which the emitter current flows approximately hpg times the base current.
8, the first wiring 57.71 through which the base current flows is made thick. 1. Rebase wiring is constructed with the minimum line width of the process.

In addition, the presence of two contacts 53, 54, 66, and 72 can be used to reduce contact resistance where there is enough room, and
This is to reduce the sheet resistance of the drain or soni of the OS transistor and increase the speed.

In this way, a two-manpower NAND circuit can be constructed.

FIG. 6 shows a sectional view of FIG. 5, which constitutes a two-man NAND circuit of the bipolar/chios composite circuit of FIG. 4.

Element numbers are given in the figure to indicate correspondence with FIG. 4. Wiring is added to the cross-sectional view shown in FIG. 3 (15) before the wiring process, and further explanation will be omitted.

Figure 7 shows the applicant's earlier application (Japanese Patent Application No. 57-188).
No. 942) This is a two-person powered NOR circuit which is another example of the bipolar/CMO8 composite circuit.

In FIG. 7, a first NPN 89 has a collector connected to the power supply terminal 90 and an emitter connected to the output terminal 81, and a collector connected to the output terminal 81 and an emitter connected to a fixed potential terminal having a ground potential. second NPN, 79 and 8
The two input terminals 82 and 83 have their gates connected to different input terminals 79 and 80, and their sources and drains connected in series between the collector and base of the first NPN 88, respectively. 1st and 2nd PMO8,8
4 and 85 are input terminals 79 whose respective gates are different from each other.
and 80, each drain and each source is a second NPN 8
The gates of the first and second NMOs 8 and 86 connected in parallel between the collector and base of 90 are connected to the power supply terminal 90.
The third NMO 8, 87 has its drain and emitter connected to the base and emitter of the first NPN 88 (16), and its gate is connected to the power supply terminal 90, and its drain and emitter are connected to the base and emitter of the second NPN 89. This is the fourth NMO 8 to be connected.

Table 2 shows the logical operation of this embodiment.

Table 2 First, when both the input cuffs 9 and 80 are at the ζ'' level, both the first and second PMOs 882 and 83 are turned on, and both the first and second NMOs 884 and 85 are turned off. The base potential of the first NPN 88 rises, and the first NP
N88 is turned on, and the base and emitter of the second ONPN89 are short-circuited via the fourth NMO8 (17) 87, which is in the non-saturation region, and the emitter current of the first NPN88 is turned off, charging the load.
The output 81 becomes 1'' level.

When either the input cuff 9 or 80 is at the "'1" level, either the first or second PMO 882, 83 is turned off, or either the first or second NMO 884, 85 is turned on. . Therefore, the base and emitter of the first NPN 88 are short-circuited through the third 8MO 886 which is in the non-saturation region and turned off, and the base and collector of the second NPN 89 are shorted when the first and second NMO 884 or 85 are turned on. Since the base of the second NPN 89 is short-circuited from the output 81, the second NPN 89 is turned on and the output 81 is at the +2 level.

When both the input cuffs 9 and 80 are at the "1# level," both the first and second PMOs 882 and 83 are turned off, and both the first and second ONMOs 884 and 85 are turned on. Therefore, the operation is the same as above. Then, the output 81 becomes the "0" level.

This two-person NOR circuit is constructed using the basic cell shown in Figure 2 (1
8) Figure 8 shows the configuration. In the figure, the X mark is the contact, the broken line is the first wiring such as A4, the z mark is the through hole,
A one-point button line is shown on the second wiring such as AL.

Since the details have been explained in FIG. 5, the numbers of the same parts as in FIG. 2 are omitted here to avoid complexity. In order to improve the correspondence with FIG. 7, element numbers are given on the gate electrodes and the like. Contacts in the same locations as in Figure 5 are indicated by the same numbers.

First wiring 52 and contact 5, which becomes the VCC power line
4,55.56 the source of the first PMO882,
Collector of first NPN88, third and fourth NMO88
Gate electrodes 6 and 87 are connected to the CC potential. 1st
The drain of the second PMO 883, the base of the first NPN 88,
The drain of the third ONMO 886 is connected. 1st
Wiring 9496 Contact 63, 64, 93, 95.67
by the emitter of the first NPN88, the third NM08
The source of 86, the drains of first and second NMOs 884 and 85, and the collector of second NPN 89 are connected (19). Further 2F; 2 wiring 68. Through hole 69
The emitter of the first NPN88 and the second NPN
A PN89 collector is connected. The reason for providing the second wiring 68 is the same as in the case of the two-man power NAND circuit described above. The sources of the first and second 8MO88485, the drain of the fourth NMO887, and the base of the second NPN89 are connected by the first wiring 97 and contacts 6672, 73, and 74. The source of the fourth 8MO 887, the emitter of the second NPN 89, and the P substrate 37 are fixed to the ground potential by contacting with the first wiring 75 serving as a ground potential line. In this way, two-man power N O
R, configure the circuit.

Figure 9 shows a bipolar CM suitable for the basic cell of this embodiment.
This is an inverter circuit that is another example of the O3 composite circuit.

In FIG. 9, 107 has a collector connected to the power supply terminal 107.
a first NPN whose emitter is connected to the output terminal 99;
, 108 are second NPNIs whose collectors are connected to the output terminal 99 and whose emitters are connected to the fixed potential terminal (20) which is at ground potential.O1 and 102 have their gates connected to the input terminal 98 and their sources and drains connected to the first The first and second PMOs 8103 and 104 connected to the collector and base of the NPN 107 have their gates connected to the input terminal 9B, and their drains and sources connected to the second NPN 107, respectively.
The first and second NMOs 8105 connected to the collector and base of the PN 108 have their gates or power supply terminals 100 connected to
The drain and source are each a first NPNI O7 (
7) Third 8MO81 connected to base and emitter
06 is a fourth 8MO8 whose gate is connected to the power supply terminal 100, and whose drain and source are connected to the base and emitter of the second NPN 108, respectively.

Table 3 (21) When input 98 is at “0# level”, first and second PM081
(11, 102 are turned on and the first and second NMO 810
3,104 is turned off. Therefore the first NPN10
The base potential of 7 rises, the first NPN'lO7 turns on, and the base and emitter of the second NPN 108 are short-circuited via the fourth NMO8106 in the non-saturation region and turns off. The emitter current of the first NPN 107 charges the load and the output 99 becomes the "1# level. When the input 98 is at the 1" level, the first and second PMO8IOI
, 102 are turned off, and the first and second NMOs 8103,1
04 is turned on. Therefore, between the base and emitter of the first NPNlo 7 is the third 8MO8 which is in the non-saturation region.
105, the first NPNI O7 is turned off, and the base and collector of the second ONPN 108 are connected to the first NPNI O7.
, are short-circuited through the second 8MO8103 and 104, so the base current is supplied from the output 99 to the base of the second NPN108, and the second NPM108 is turned on,
Output 99 becomes "0" level. 3rd and 4th 8MO8
12 and 13 act as a substitute for the resistor (22), and when the first and second NPNs are turned on, they somewhat shunt the base current, but the first and second NPNs
When the PN is turned off, both operate in the non-saturated region.The drain and source have the same potential and work to quickly draw out the accumulated charge.

FIG. 10 shows this inverter circuit constructed using the basic cell shown in FIG. 2. In the figure, 2 marks indicate contacts, broken lines indicate first wiring, Z marks indicate through balls, and dashed lines indicate second wiring. In order to correspond to FIG. 9, element numbers are given on the gate electrodes and the like. Also, contacts etc. in the same locations as in FIGS. 5 and 8 are indicated by the same numbers.

First, the first wiring 52 which becomes the VI'C power line and the contacts 53, 54, 55.
The source of the IOI, 102, the collector of the first NPN 107, the gate electrode of the third, 46th') NMO 8105, 106 are connected to the V C,:C potential.

First wiring 57 and contacts 59, 58.
The drain of the third (7) NMO8 (23) 105 is connected. The first wiring 94°96 and the contacts 63, 64, 93, 95.67
The emitter of the NPN 107, the source of the third NMO 8105, the drains of the first and second NMO 8103°104, and the collector of the second NPNI O8 are connected. Further, the emitter of the first NPN 107 and the collector of the second NPN 10B are connected by a second wiring 68 and through holes 69,70. The reason is the same as in the case of the two-person NAND circuit described above. First wiring 97, contact 66
．． 72, 73° 74 by the first and second NMO810
The source of No. 3,104, the drain of the fourth NMO 8106, and the base of the second NPN 108 are connected. The emitter of the second NPNl 08 and the fourth NMO
The source of 8106 and substrate 37 are fixed at ground potential. Further, first wirings 111, 112 and contacts 109, 1
10 by 1st, 2nd PMO 8, 1st, 2nd NM
The gate of O8 is connected. In this way, the inverter circuit is constructed.

(24) The inverter circuit, two-man power NA, ND circuit, two-man power NOR, and circuit configuration methods have been explained in detail above, but the rainbow feature of the pattern of the basic cell of this example is: The main feature is that there is space for one or more internal wirings on both sides of the board. This space is essential when constructing a complex logic circuit using a large number of basic cells.8 When constructing a complex logic circuit, NPN bivore
It is sufficient to use the la transistor only in the part of the basic cell that is output to the wiring channel. Therefore, when interconnecting adjacent basic cells with the first interconnect, the first interconnect passes over an unused NPN bipolar transistor, so it is better to change the first insulating film for each type of contact.

Furthermore, in this embodiment, in the basic cell, two PMO transistors are connected in series to two NPN bipolar transistors.
8, NMO8 pairs are provided, but three or four may not be connected in series.

One bear of sweet PMO8 and NMO8 is fine.

As described above, according to this embodiment, it is possible to realize a gate array LSI having basic cells that can configure high-speed, low-power consumption (25) bipolar/CMO8 complex logic circuits at high density. A gate array LSI can be obtained.

FIG. 11 shows another embodiment of the invention. The same parts and corresponding parts as in FIG. 2 are indicated by the same numbers. The difference from FIG. 2 is that the emitter region 26 constituting the NPN bipolar transistor in the N well 21 is not changed to the collector region 26.
This is a point that is close to .

The emitter region 29 in the N-well 22 is also moved closer to the collector region 27. This reduces collector resistance and increases speed. Next, one or more dog bones with which contact can be made are provided at intermediate locations other than at both ends of the gate electrodes 35 and 36. This makes it easier to construct complex logic gates.

Next, the base region 28 in the N-well 22 is made vertical to reduce the size of the basic cell in the X direction. This allows the degree of integration to be further increased.

FIG. 12 shows a two-man power NAND circuit constructed by using this basic cell to form a Bibo (26) LA/CMO8 composite shown in FIG. 4. In the figure, old marks indicate contacts, broken lines indicate first wiring, old marks indicate through holes, and dashed lines indicate second wiring. The same parts and corresponding parts as in FIG. 11 are indicated by the same numbers, and element numbers are given to gate electrodes and the like to correspond to those in FIG.

The sources of the first and second PMOs 844 and 45, the gate electrode of NM0848.49, and the collector of the first NPN 50 are Connected to electrical potential. First wiring 118 and contacts 119, 12
Drains of first and second PMO844,45 by 0,121, first NPN500 base, third NMO8
48 drains are connected. 1st wiring 1.22,12
3 and contacts 124, 125, 126, 127°12
8, the emitter of the first NPN 50, the first ONM
The drain of O846, the collector of second NPN51, and the source of third NM084B are connected. Furthermore, the second m
129, through hole 130 (27) 131 connects the emitter of the first NPN 50 and the second NPN
The collector of PN51 is connected. The reason is the same as explained in FIG. The source of the second NMO 847, the drain of the fourth NMO 849, and the second NPN
510 base is connected. The emitter of the second NPN 51, the source of the fourth NMO 849, and the P substrate 37 are fixed to the ground potential by the first wiring 136 serving as a ground potential line and contacts 137, 138, and 139. In this way, a two-person NAND circuit is constructed.

According to this embodiment, even faster and more highly integrated gate array L
SI can be obtained.

In the above explanation, we have described the basic cell that can configure a one-time one-channel value as shown in Japanese Patent Application No. 188942/1986 as a bipolar/CM'O8 compound logic circuit, but other bipolar/MO8 compound logic circuits can also be used. A basic cell can be configured using a similar idea.

Although the description of this embodiment has focused on the gate array L-8I, it is obvious that this idea can also be applied to cells of general custom LSIs.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to manufacture an LSI having cells that can be configured in high density, thereby realizing a high-speed, low power consumption, highly integrated semiconductor integrated circuit device.

[Brief explanation of the drawing]

Fig. 1 is a chip diagram of a gate array LSI, Fig. 2 (%1) is a diagram showing a planar pattern of a basic cell showing an embodiment of the present invention, Fig. 3 is a vertical structure diagram of Fig. 2, and Fig. 4 is bipolar·
A two-man NAND circuit diagram that is an example of a CMO8 composite circuit, Figure 5 is a diagram showing a planar pattern configuring the circuit in Figure 4 using the basic cells shown in Figure 2 (9), and Figure 6 is a diagram shown in Figure 5. The vertical structure diagram in Figure 7 is an example of a bipolar CMO86 combination circuit, which is a two-man power N. R circuit diagram, FIG. 8 is a diagram showing a plane pattern configuring the circuit of FIG. 7 using the basic cell shown in FIG. 2, FIG. 9 is an inverter circuit diagram which is an example of a bipolar CMO8 composite circuit, and FIG. The diagram shows the base shown in Figure 2 (29).A plane pattern diagram of the circuit shown in Figure 9 in this cell.
FIG. 1 is a plan pattern diagram of a basic cell showing another embodiment of the present invention, and FIG. 12 is a plan pattern diagram of the basic cell shown in FIG. 11 constituting the circuit of FIG. 4. 11... Basic cell, 21.22... N well, 23
... P+ area of PMO8, 24... collector area,
25...Base region, 26...Emitter region, 27
...Collector area, 28...Base area, 29...
- Emitter region, 30...N+ region 33 of NMO8
...The potential of the P substrate is (30)

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device comprising a plurality of basic cells each consisting of a plurality of bipolar transistors and a plurality of MOS transistors, a bipolar transistor and a MOS whose one main terminal is fixed at the highest potential of a semiconductor substrate ) are arranged in the same well provided on the main surface of the semiconductor substrate, the potential of the well is supplied from the one main terminal, and the potential of the one main terminal changes during circuit operation. A semiconductor integrated circuit device, wherein the bipolar transistor is arranged in a well different from the well, and another MOS transistor is arranged between the two wells to constitute a basic cell. 2. In claim 1, the other main terminal of the bipolar transistor is fixed at the highest potential in the semiconductor substrate, and the potential of the one main terminal changes during circuit operation. A semiconductor integrated circuit device characterized in that one main terminal of another bipolar transistor is connected to a metal low resistance wiring. 3. A semiconductor integrated circuit according to claim 1 and claim 2, characterized in that a first insulating film on the drain or source of at least one MOS transistor is provided with a plurality of contacts. Device. 4. A semiconductor integrated circuit device according to claim 1 or 2, wherein the wiring connected to the control terminal of the bipolar transistor is thinner than the wiring connected to the other main terminal. 5. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that no base contact is provided between one main terminal and the other main terminal of the bipolar transistor. 6. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that the semiconductor integrated circuit device is a gate array LSI. 7. In claim 1 or 2, MO
S) A semiconductor integrated circuit @ installation, characterized in that an input to a transistor and an output of one main terminal of a bipolar transistor whose potential changes during circuit operation are on a wiring grid. 8. A semiconductor integrated circuit device according to claim 6, characterized in that a bulge capable of contacting wiring is provided at one or more locations on the gate electrode of the MOS transistor. 9. In claim 6, KNP in the basic cell
N) 2 transistors, PMO8) transistor and NMC
15 A semiconductor integrated circuit device comprising at least one l-transistor pair. 10. Permissible range of requirements In item 6, the device is characterized by providing passage spaces for one or more logic circuits on both sides of the highest potential power supply wiring and the lowest potential power supply wiring that pass over the MOS transistor. Semiconductor integrated circuit device.