JPH0546104B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to semiconductor large-scale integrated circuits, and in particular,
High speed, low power consumption gate array LSI consisting of CMOS transistors and bipolar transistors
Regarding. A gate array LSI is a device that manufactures an LSI with the desired electrical circuit operation by creating only the mask corresponding to the wiring out of the ten or so photomasks used when manufacturing the LSI according to the product being developed.
It is said that the concept of this master slice method has been around since the 1960s. Figure 1 shows the configuration of the gate array LSI. The LSI chip 10 has a bonding pad and an input/output circuit area 14 on its outer periphery, and inside it, basic cell rows 12 in which basic cells 11 consisting of elements such as transistors are arranged in the x-axis direction are repeated with a wiring area 13 in between. It has a laid out configuration. In order to obtain the desired electrical circuit operation, adjacent basic cells 1
One or several 1's are connected to form a NAND gate, flip-flop, etc. One LSI is constructed by wiring various logic gates formed by a plurality of basic cells 11 according to a logic diagram. In a conventional CMOS gate array LSI, the basic cell 11 is composed of CMOS transistors.
CMOS circuits have the advantage of low power consumption, but because the transfer conductance of MOS transistors is small, charging and discharging takes time when the load capacitance is large, resulting in slow speed. Furthermore, in the conventional bipolar gate array LSI, the basic cell 11 is composed of a bipolar transistor, a resistor, and the like. In bipolar circuits, the transfer conductance of bipolar transistors is larger than that of MOS transistors, so
Although it has the advantage of not slowing down even when the load capacity increases, it has the disadvantage of high power consumption because large currents are passed into and out of low-impedance circuits. An object of the present invention is to compensate for the drawbacks of the MOS gate array LSI and bipolar gate array LSI described above, and to provide a high-speed, low power consumption gate array LSI. The present invention focuses on the low power consumption characteristics of CMOS circuits and the high speed characteristics of bipolar circuits, and uses a composite circuit that combines both circuits as a basic cell.
The aim is to obtain a gate array LSI with high speed and low power consumption. Therefore, the basic cell is a composite circuit in which the output stage is made up of bipolar transistors and the logic circuit and the circuit that drives the bipolar transistors are made up of CMOS circuits. Hereinafter, the present invention will be explained in detail with reference to Examples. Figure 2 shows a totem pole output type 2-input NAND
Shows the circuit. In FIG. 2, 20 is a first NPN transistor (hereinafter abbreviated as NPN) whose collector is connected to the power supply terminal 203 and whose emitter is connected to the output terminal 202;
21 is a second NPN whose collector is connected to the output terminal 202 and whose emitter is connected to a fixed potential terminal whose ground potential is GND; 201 is the two input terminals;
and 23, each gate is connected to a different input terminal 201, each source and each drain is connected to a first
The PMOSs 26 and 27 are connected in parallel between the collector and base of the NPN 20, with each gate connected to a different input terminal 201, and each drain and each source connected between the collector and base of the second NPN 21. each connected in series
NMOS, 210 and 211 are the first and second
This is a resistor provided between the base and emitter of the NPNs 20 and 21. Table 1 shows the logical operation of this embodiment.

[Table] First, when either input 201 is at the “0” level, either PMOS 22 or 23 is turned on.
Either NMOS 26 or 27 is turned off. Therefore, the base potential of the first NPN 20 increases,
The first NPN 20 is turned on and the second NPN 21
Since the base and emitter are short-circuited through the resistor 211 and turned off, the emitter current of the first NPN 20 charges the load and the output 202 becomes the "1" level. When both inputs 201 are at “0” level,
Both PMOS22 and 23 are turned on, and NMOS
Both 26 and 27 are turned off. Therefore, the operation is the same as above and the output 202 becomes "1". On the other hand, when both inputs 201 are at "1" level,
Both PMOS22 and 23 are turned off, and NMOS
Both 26 and 27 are turned on. Therefore, the first
NPN20 has a resistance of 210 between the base and emitter.
is shorted and turned off through the second NPN21.
Since the base and collector of the second NPN 21 are short-circuited via the NMOS 26 and 27, current is supplied to the base of the second NPN 21 from the output 202, and the second
The NPN 21 is turned on, and the output 202 becomes the "0" level. Resistors 210 and 211 serve to shunt the base current when the NPN transistor is turned on, but to drain the accumulated charge when the NPN transistor is turned off. According to this embodiment, a two-input NAND circuit can be realized with a minimum configuration of CMOS and bipolar transistors. Further, according to this embodiment, since an NPN bipolar transistor with excellent high frequency characteristics is used, ultra high-speed operation is possible. Further, according to this embodiment, a circuit with high input impedance and low output impedance can be realized, and since no conductive path is created from the power supply 203 to the ground, low power consumption characteristics can be realized. A layout pattern that can suitably configure this bipolar/CMOS composite circuit is shown in FIG. 3, and a vertical structure is shown in FIG. 4 to aid understanding. FIG. 4 shows an inverter circuit, and common concepts are represented by the same symbols as in FIG. In FIG. 3, the pattern of the buried layer 227 in FIG. 4 is omitted for the sake of brevity. isolation 2
PMOS22, 23, NPN20, resistor 2 in 12
10, 211 and NMOS 26, 27,
The NPN 21 is configured within the isolation 213. A second electrode is placed on the gate electrodes 220 and 221 in FIG.
The number of the MOS transistor corresponding to the figure is shown.
From P ⁺ region 219 and gate electrodes 220, 221
PMOS22 and 23 are configured, and P well 214
N ⁺ region 223 and gate electrodes 221, 220
The NMOS 26 and 27 are configured from the above. NPN20
is based on P area 217, and inside P area 217
The N ⁺ region 218 is used as an emitter, and the N ⁺ region 215 is used as a collector. Resistors 210 and 211 are constructed from P regions 216 and 222, respectively.
NPN21 is a P in isolation 213
Based on region 225, N ⁺ in P region 225
The region 226 is used as an emitter, and the N ⁺ region 224 is used as a collector. Next, the connections between each element will be explained. NPN
The collector 215 of PMOS 20 and the sources of PMOS 22 and 23 are connected to the power supply by AL wiring 42.
□×marks indicate contacts between the AL wiring and each element. The drains of the PMOSs 22 and 23, the base of the NPN 20, and one end of the resistor 210 are connected to each other by AL wiring 228. The other end of the resistor 210
The emitter 218 of the NPN 20 is connected by an AL wiring 229. The emitter 226 of the NPN 21, one end of the resistor 211, and the P well 214 are the AL wiring 4
3 to ground potential. The other end of the resistor 211, the source of the NMOS 27, and the base of the NPN 21 are connected by AL wiring 230, respectively. The drain of the NMOS 26 and the collector 224 of the NPN 21 are connected by an AL wiring 231. Although not shown, the emitter 218 of NPN20
The NPN 21 and the collector 224 are connected by the second layer AL wiring. FIG. 5 shows a pattern obtained by removing the AL wiring and contacts from the layout pattern shown in FIG. 3. In other words, if the pattern in FIG. 5 is contacted with the AL wiring shown in FIG. 3, a 2-input NAND circuit can be obtained, and if it is contacted with other AL wiring, an inverter or 2-input NOR circuit can be constructed.
Furthermore, when configuring a flip-flop etc., the fifth
The required number of patterns shown in the figure can be used by arranging them horizontally.
Therefore, if the basic cells shown in FIG. 5 are arranged as shown in FIG. 1, a basic cell row of a gate array can be constructed. According to this embodiment, it is possible to realize a gate array LSI having basic cells that can configure a bipolar/CMOS complex logic circuit.
A high-speed, low-power consumption gate array LSI can be obtained. Figure 6 shows totem pole output type 2-input NAND
Another example of the circuit is shown. The resistor 210 in the embodiment of FIG. 2 is replaced with NMOS 240 and PMOS 242,
This is an example in which the resistor 211 is replaced with an NMOS 241. The gate of NMOS240 is the power supply terminal 20
3, the drain and source are each NPN20
is connected to the base and emitter. NMOS24
The gate of NPN 21 is connected to the power supply terminal 203, and the drain and source are connected to the base and emitter of NPN 21, respectively. The gate of PMOS 242 is connected to ground potential, and the drain and source are connected to the emitter and base of NPN 20, respectively. Parts that are the same as in Figure 2 are designated by the same numbers. The operation is almost the same as in FIG. NMOS241 always operates in the non-saturation region,
It is used as a substitute for resistor 211. The PMOS 242 functions to raise the output 202 to the power supply voltage when either input 201 is at the "0" level.
When the output 202 of the NMOS 240 is at “0” level,
Short-circuit between the base and emitter of NPN20, and
20 is turned off, eliminating through current and reducing power consumption. According to this embodiment, since a MOS transistor having a small channel width is used instead of a resistor, it is possible to further improve the degree of integration. FIG. 7 shows a layout pattern that can suitably configure this bipolar/CMOS composite circuit. In FIG. 7, the patterns of the buried layer and the like are omitted for the sake of brevity. PMOS2 in isolation 243
2,23,242, NPN20 and NMOS26,
27, 240, and 241, and an NPN 21 is configured within the isolation 244. MOS transistor numbers corresponding to those in FIG. 6 are shown on the gate electrodes 253, 254, 255, and 256. From P ⁺ region 249 and gate electrodes 253, 254, 255
PMOS 242, 23, 22 are configured, and N ⁺ region 250 in P well 245 and gate electrode 254,
255 constitutes NMOS 26 and 27. In addition, N ⁺ regions 251 and 252 in the P well 245
and NMOS240,241 from the gate electrode 256
is configured. The NPN 20 has a P region 247 as a base, an N ⁺ region 248 in the P region 247 as an emitter, and an N ⁺ region 246 as a collector.
NPN21 is a P in isolation 244
Based on region 258, N ⁺ in P region 258
The region 259 is used as an emitter, and the N ⁺ region 257 is used as a collector. Next, the connections between each element will be explained. NPN
The collector 246 of 20, the sources of PMOS 22 and 23, and the gates 256 of NMOS 240 and 241 are
It is connected to the power supply by AL wiring 42. □× in the diagram
The marks indicate contacts between the AL wiring and each element.
The drains of PMOS22 and 23, the base 247 of NPN20, and the source of PMOS242 are the AL wiring 26
Each is connected by a 0. The emitter 248 of NPN20 and the drain of PMOS242 are AL wiring 2
61. The drain of the PMOS 242, the drain of the NMOS 26, and the source of the NMOS 240 are connected by an AL wiring 262.
Drain of NMOS26 and collector 2 of NPN21
57 is connected by an AL wiring 263.
The source of the NMOS 27, the drain of the NMOS 241, and the base 258 of the NPN 21 are connected to each other by an AL wiring 264. Emitsuta 25 of NPN21
9, the source of the NMOS 241, the gate 253 of the PMOS 242, and the P well 245 are connected to the ground potential by the AL wiring 43. FIG. 8 shows a pattern obtained by removing the AL wiring and contacts from the layout pattern shown in FIG. 7. In other words, if the pattern shown in FIG. 8 is contacted with the AL wiring shown in FIG. 7, a 2-input NAND circuit can be obtained, and if it is contacted with other AL wiring, an inverter or a 2-input NOR circuit can be constructed.
Furthermore, when configuring a flip-flop etc., the eighth
The required number of patterns shown in the figure can be used by arranging them horizontally.
Therefore, if the basic cells shown in FIG. 8 are arranged as shown in FIG. 1, a basic cell row of a gate array can be constructed. According to this embodiment, since a MOS transistor with a small channel width is used instead of a resistor, a highly integrated gate array can be achieved.
You can get LSI. In the embodiment shown in FIG. 6, the base of NPN20,
I installed PMOS242 between the emitters, but this
There is no problem in actual operation even if the PMOS 242 is not provided. This allows for even more highly integrated gate array LSI
can be obtained. Figure 9 shows two inputs with a totem pole output stage.
Another embodiment of the NAND circuit will be shown. This NAND circuit consists of NPNs 20 and 21, PMOSs 22 and 23, depletion type NMOS transistors (hereinafter abbreviated as DNMOS) 24 and 25, NMOS 26 and 27, and depletion type PMOS transistors (hereinafter abbreviated as DPMOS) 28 and 29. Explain the operation. First, when either input 201 is at “0” level,
Either PMOS22 or 23 turns on,
Either NMOS26 or 27 is turned off,
The on-resistance of either DPMOS 28 or 29 becomes smaller. Therefore, the base potential of NPN20 rises, NPN20 turns on, and NPN21 turns on.
Since the base and emitter are short-circuited via DPMOS 28 or 29 and turned off, the emitter current of NPN 20 charges the load and the output 202 becomes level "1". When both inputs 201 are at “0” level,
Both PMOS22 and 23 are turned on, and NMOS
Both 26 and 27 are turned off, and DPMOS28,
The on-resistance of No. 29 is reduced. Therefore, the operation is the same as above, and the output 202 is at the "1" level.
On the other hand, when both inputs 201 are at "1" level,
Both PMOS22 and 23 are turned off, and NMOS
Both 26 and 27 are turned on, and DNMOS24,
The on-resistance of 25 becomes smaller, and the DPMOS28,2
The on-resistance of No. 9 increases. Therefore, NPN2
0 is the base and between the emitters is DNMOS24,25
Since the base and collector of NPN21 are short-circuited via NMOS26 and 27, the output 20 is connected to the base of NPN21.
Current is supplied from 2, NPN21 turns on,
Output 202 becomes "0" level. According to this embodiment, when turning off the NPN,
The on-resistance of the MOS between the base and emitter of the NPN becomes small, and the accumulated charge is removed quickly, and when the NPN turns on, the MOS on-resistance between the base and emitter becomes smaller.
The on-resistance of the MOS increases, and the base current is not shunted, so it turns on quickly. Therefore, higher speed operation is possible. A layout pattern that can suitably configure this bipolar/CMOS composite circuit is shown in Figure 10.
The vertical structure is shown in FIG. 11 to aid understanding. FIG. 11 shows an inverter circuit, and common concepts are represented by the same symbols as in FIG. In FIG. 10, the buried layer 50 pattern and the like in FIG. 11 are omitted for brevity. PMOS22 in isolation 30,
23, DNMOS 24, 25, and NPN 20 are configured, and NMOS 26,
27, configures DPMOS28, 29 and NPN21. 9 on the gate electrodes 37 and 38 in FIG.
The number of the MOS transistor corresponding to the figure is shown.
PMOS from P ⁺ region 34 and gate electrodes 38 and 37
22 and 23 are configured, and NMOS 26 and 27 are configured from the N ⁺ region 35 and gate electrodes 38 and 37,
DNMOS 24 and 25 are formed from an N ⁺ region 33 and gate electrodes 37 and 38 on the PMOS side outside of these, and a P ⁺ region 36 and gate electrodes 37 and 38 on the NMOS side.
DPMOS 28 and 29 are configured from 38.
The NPN 20 uses the N ⁺ region 39 in the isolation 30 as a collector, the P well 31 as a base, and the source of the DNMOS 25 (where the contact hole 41 in FIG. 10 is located) as an emitter.
The P-well 31 includes the DNMOSs 24 and 25, and also includes part of the drain regions of the PMOSs 22 and 23. This is to internally connect the base of the NPN 20 and the drains of the PMOS 22 and 23 without using AL wiring. The NPN 21 uses the N ⁺ region 40 in the isolation 44 as an emitter, the P well 32 as the base, and the NMOS
The outside 45 of the P well 32 of the drain of No. 26 is used as the collector. P well 32 is DPMOS28,
Contains some of the 29 sources. This is NPN
Between the base of 21 and the sources of DPMOS28 and 29
This is for internal connection without using AL wiring. Furthermore, the P-well 32 does not include a part of the drain of the NMOS 26. This is the collector of NPN21
This is to internally connect the drains of the NMOS 26 without using AL wiring. NPN20 collector 3
9 and the sources of PMOS22 and 23 are VCC power supply line 4
2 to the power supply. The base of the NPN 20 and the drain of the DNMOS 24 are connected by an AL wiring 46. NPN21 emitter 40 and DPMOS
The drains of 28 and 29 are connected to GND by a GND power line 43. NPN21 base and
The source of the NMOS 27 is connected to the AL wiring 47. Emitter of NPN20 (at contact hole 41) and collector of NPN21 (at contact hole 4)
8) is connected to the second layer AL (not shown), this becomes the output 202. Input 201 is gate electrode 37,38. By using the necessary number of layout patterns shown in FIG. 10 and changing the AL wiring layer and contact layer for each logic gate, an inverter or a NAND circuit can be constructed. Therefore, if the cell shown in FIG. 10 without the AL wiring layer and contact layer is arranged as a basic cell as shown in FIG. 1, it becomes a basic cell row of a gate array. Also, DNMOS24,2
Contact holes connecting the source and drain regions of 5 and the AL wiring, and the sources of PDMOS28 and 29,
Since the contact hole connecting the drain region and the AL wiring can exist near the center of the basic cell,
The areas on the outside of the source and drain regions of the DNMOS 24 and 25 and the DPMOS 28 and 29 can be used as an AL wiring region. This corresponds to burying the element under the wiring area, and improves the area efficiency. According to this embodiment, bipolar
Since CMOS complex logic circuits can be configured with high density,
High speed, low power consumption and high integration bipolar
A CMOS composite gate array LSI can be obtained. Other embodiments of the invention will be described with reference to the drawings. FIG. 12 shows a two-input NAND circuit with complementary output stages. This NAND circuit includes a PNP transistor (hereinafter abbreviated as PNP) 51, NPN21, PMOS22,
23, DNMOS24, 25, NMOS26, 27,
Consists of DPMOS28 and 29. Components that are the same as in FIG. 2 are designated by the same reference numerals. Next, the operation will be explained.
First, when either input 52 is at the “0” level,
Either PMOS22 or 23 turns on,
Either NMOS26 or 27 is turned off,
The on-resistance of either DPMOS 28 or 29 becomes smaller. Therefore, the base potential of PNP51 decreases, PNP51 turns on, and NPN21 becomes
Since the base and emitter are short-circuited via DPMOS 28 or 29 and turned off, the collector current of PNP 51 charges the load and the output 53 becomes the "1" level. Next, when both inputs 52 are at “0” level,
Both PMOS22 and 23 are turned on, and NMOS
Both 26 and 27 are turned off, and DPMOS28,
The on-resistance of No. 29 is reduced. Therefore, the operation is the same as above, and the output 53 is at the "1" level. On the other hand, when both inputs 52 are at “1” level, PMOS
Both 22 and 23 are turned off, and NMOS26,
Both 27 are turned on, and DNMOS24, 25
The on-resistance of DPMOS 28 and 29 becomes larger. Therefore, the base and emitter of PNP51 are short-circuited through DNMOS24 and 25, and the base and emitter of PNP51 are turned off.
Since the collectors are short-circuited via the NMOS 26 and 27, a current is supplied to the base of the NPN 21 from the output 53, the NPN 21 is turned on, and the output 53 becomes the "0" level. A layout pattern that can suitably configure this bipolar/CMOS composite circuit is shown in Figure 13.
The vertical structure is shown in FIG. 14 to aid understanding. Although FIG. 14 shows an inverter circuit, common concepts are indicated by the same numbers as in FIG. 13. For simplicity, FIG. 13 omits the pattern of the buried layer 50 in FIG. 14. In this example, the PNP transistor 51
The horizontal form is used. Gate electrodes 37, 38
The numbers of the MOS transistors corresponding to those in FIG. 12 are shown above. The configurations of the MOS transistor and NPN 21 are the same as in FIG. The PNP 51 is horizontal, with the P ⁺ region 62 as the emitter, the N region in the isolation 60 as the base, and the PMOS 22 as the base.
The drain (where the contact hole 63 is located) is used as the collector. P-well 61 is DNMOS2
Does not include some of the sources in item 4. This is PNP
This is to internally connect the base of DNMOS 51 and the source of DNMOS 24 without using AL wiring. PNP5
The emitter 62 of 1 and the drain of DNMOS 25 are
It is connected to a power supply by a VCC power line 42.
The source of the DNMOS 24 and the sources of the PMOS 22 and 23 are connected by an AL wiring 64. NMOS
The connections of 26, 27, DPMOS 28, 29, and NPN 21 are the same as those shown in FIG. 10, so their explanation will be omitted. PNP51 collector (contact hole 63) and NPN21 collector (contact hole 4)
8) is connected to the second layer AL (not shown), the output becomes 53. Input 52 is gate electrode 37,38. By using the necessary number of layout patterns shown in FIG. 13 and changing the AL wiring layer and contact layer for each logic gate, an inverter or a NAND circuit can be constructed. Therefore, if the cell shown in FIG. 13 without the AL wiring layer and contact layer is used as a basic cell and arranged as shown in FIG. 1, it becomes the basic cell row of the gate array. Also in this embodiment, high speed,
A bipolar/CMOS composite gate array LSI with low power consumption and high integration can be obtained. 2 inputs with complementary output stages shown in Figure 15
Another embodiment of the present invention that can suitably configure a NAND circuit is shown in FIG. 16, and a vertical structure is shown in FIG. 17 for easier understanding. First, the operation shown in FIG. 15 will be explained. First, when either input 86 is at the “0” level, which PMOS 82 or 83 is turned on,
Either NMOS 84 or 85 is turned off. Therefore, the base potentials of NPN 80 and PNP 81 rise, NPN 80 is turned on, and PNP 81 is turned off, so that the emitter current of NPN 80 charges the load and the output 87 becomes the "1" level. Next input 86
When both are at “0” level, PMOS82, 83
are both turned on, and both NMOS 84 and 85 are turned on. Therefore, the operation is the same as above, and the output 87 is at the "1" level. On the other hand, when both inputs 86 are at the "1" level, both PMOSs 82 and 83 are turned off, and both NMOSs 84 and 85 are turned on. Therefore, the base potential of NPN80 and PNP81 decreases, and NPN80 turns off.
Since PNP81 is turned on, output 87 is “0”
level. FIG. 16 shows a layout pattern that can suitably configure FIG. 15, and FIG. 17 shows its vertical structure. FIG. 17 shows an inverter circuit, and common concepts are represented by the same symbols as in FIG. 16.
The numbers of the MOS transistors corresponding to those in FIG. 15 are shown on the gate electrodes 93 and 94 in FIG. 16. PMOS 83 from P ⁺ region 91 and gate electrodes 93 and 94,
82 is composed of an N ⁺ region 92 and a gate electrode 93,
NMOS 84 and 85 are configured from 94. NPN
80 uses the N ⁺ region 96 as an emitter, and the P region 95
is the base, and the N ⁺ region 99 is the collector. In addition, PNP81 uses P ⁺ region 98 as an emitter,
The N region 97 is the base, and the P ⁺ region 100 is the collector. PMOS82, 83 source and
A collector 99 of the NPN 80 is connected to a power supply via a VCC power line 101. Drains of PMOS82 and 83, bases 95 and 97 of NPN80 and PNP81,
The drains of the NMOS 84 are connected by an AL wiring 102. PNP81 collector 100 and
The source of NMOS85 is GND power line 103
Connected to GND. NPN80 Emitsuta96 and
The emitters 98 of the PNP 81 are connected by an AL wiring 104, which becomes an output 87. Input 86 is gate electrode 93,94. By using the necessary number of layout patterns shown in FIG. 16 and changing the AL wiring layer and contact layer for each logic gate, an inverter or a NAND circuit can be constructed. Therefore, if the cell shown in FIG. 16 without the AL wiring layer and contact layer is used as a basic cell and arranged as shown in FIG. 1, it becomes the basic cell row of the gate array. According to this embodiment, since an isolation region is not required, a gate array LSI with even higher integration can be obtained. According to the present invention, it is possible to manufacture a gate array LSI having basic cells that can configure a bipolar/CMOS composite circuit that has both the high driving ability of a bipolar transistor circuit and the low power consumption characteristics of a CMOS circuit. gate array
LSI can be realized.

[Brief explanation of the drawing]

Fig. 1 is a chip diagram of a gate array LSI, Fig. 2 is a bipolar/CMOS composite 2-input NAND circuit diagram, and Fig. 3 is a basic cell showing an embodiment of the present invention, and a pattern configuring the circuit in Fig. 2. , Figure 4 is the third
Fig. 5 is a basic cell showing an embodiment of the present invention, Fig. 6 is a bipolar/CMOS composite 2-input NAND circuit diagram, and Fig. 7 is a basic cell showing an embodiment of the present invention. The pattern configuring the circuit shown in Figure 6, Figure 8 shows the basic cell showing an embodiment of the present invention, and Figure 9 shows the two-input bipolar/CMOS composite.
A NAND circuit diagram, Fig. 10 is a basic cell showing one embodiment of the present invention, and a pattern constituting the circuit of Fig. 9, Fig. 11 is a vertical structure diagram of Fig. 10, and Fig. 12 is a bipolar/CMOS composite circuit diagram. 2-input NAND circuit diagram,
FIG. 13 shows a basic cell showing an embodiment of the present invention, and a pattern constituting the circuit of FIG. 12, FIG. 14 is a vertical structure diagram of FIG. 13, and FIG. 15 is a bipolar
A CMOS composite 2-input NAND circuit diagram, FIG. 16 is a basic cell pattern showing an embodiment of the present invention and constitutes the circuit of FIG. 15, and FIG. 17 is a vertical structure diagram of FIG. 16. 11... Basic cell, 20... NPN transistor, 21... NPN transistor, 51... PNP
Transistor, 22, 23... PMOS transistor, 24, 25... Depletion type NMOS transistor, 26, 27, 240, 241...
NMOS transistor, 28, 29...Depression type PMOS transistor, 210, 211...
…resistance.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device constituting a gate array LSI, at least one basic cell constituting various logic gates includes a bipolar transistor constituting an output stage of the logic gate, and a MOS driving the bipolar transistor.
A semiconductor integrated circuit device comprising: a transistor; and means for extracting base charge of the bipolar transistor. 2. In claim 1, a MOS that drives the bipolar transistor
A semiconductor integrated circuit device characterized in that the transistor is a CMOS transistor. 3 In claim 1, the basic cell has a collector connected to a power supply terminal,
a first NPN bipolar transistor whose emitter is connected to the output terminal; a second NPN bipolar transistor whose collector is connected to the output terminal and whose emitter is connected to the fixed power supply terminal; whose gate is connected to the input terminal, and the source and a P-type field effect transistor whose drain is connected to the collector and base of the first NPN bipolar transistor, respectively; a P-type field effect transistor whose gate is connected to the input terminal, and whose drain and source are connected to the collector and base of the second NPN bipolar transistor, respectively; a semiconductor integrated circuit comprising: an N-type field effect transistor connected to the base; and means for extracting accumulated charge from a base connected to the base of at least one of the first and second NPN bipolar transistors. Device. 4. The semiconductor integrated circuit device according to claim 3, wherein a resistor is connected between the base and emitter of at least one of the first and second NPN bipolar transistors. 5. The semiconductor integrated circuit device according to claim 3, wherein a field effect transistor is connected to the base of at least one of the first and second NPN bipolar transistors. 6. In claim 3, a second NPN transistor whose gate is connected to the power supply terminal and whose drain and source are respectively connected to the base and emitter of the first NPN bipolar transistor
1. A semiconductor integrated circuit device comprising a type field effect transistor. 7. In claim 3, a second NPN bipolar transistor whose gate is connected to the fixed potential terminal and whose drain and source are respectively connected to the base and emitter of the first NPN bipolar transistor
A semiconductor integrated circuit device comprising a P-type field effect transistor. 8 In claim 3, a third NPN transistor whose gate is connected to the power supply terminal and whose drain and source are respectively connected to the base and emitter of the second NPN bipolar transistor
1. A semiconductor integrated circuit device comprising a type field effect transistor. 9. In claim 3, a fourth NPN transistor whose gate is connected to the input terminal and whose drain and source are respectively connected to the base and emitter of the first NPN bipolar transistor
1. A semiconductor integrated circuit device comprising a type field effect transistor. 10 In claim 3, a third P transistor whose gate is connected to the power supply terminal and whose drain and source are respectively connected to the base and emitter of the second NPN bipolar transistor
1. A semiconductor integrated circuit device comprising a type field effect transistor.