JPH04355956A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a semiconductor integrated circuit device to be enhanced in operation speed, lessened in power consumption, and increased in degree of density by a method wherein a bipolar transistor is a vertical type electrolytically dissociated from a P-type substrate, and a base region is isolated from the drain and the source region of a MOS. CONSTITUTION:A collector 215 of an NPN 20 and the sources of PMOSs 22 and 23 are connected to a power supply with an Al wiring 42. The drains of the PMOSs 22 and 23 and the base of the NPN 20 and one end of a resistor 210 are connected together with an Al wiring 228. The other end of the resistor 210 is connected to the emitter 218 of the NPN 20 with the Al wiring 228. The emitter 226 of an NPN 21, one end of a resistor 211, and a well 214 are connected to a ground potential with an Al wiring 43. The other end of the resistor 211, the source of an NMOS 27, and the base of the NPN 21 are connected together with an Al wiring 230. The drain of an NMOS 26 and the collector 224 of the NPN 21 are connected to each other with an Al wiring 231.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a device structure of a bipolar MOS composite LSI consisting of a composite circuit of MOS transistors and bipolar transistors.

0002

2. Description of the Related Art In conventional CMOS LSIs, basic cells are composed of CMOS transistors. CMOS
The circuit has the advantage of low power consumption, but M
Because the transfer conductance of the OS transistor is small,
If the load capacity is large, charging and discharging takes time, resulting in a slow speed.

Furthermore, in conventional bipolar LSIs, basic cells are composed of bipolar transistors, resistors, and the like. Bipolar circuits have the advantage of not slowing down even when the load capacitance increases because the transfer conductance of bipolar transistors is larger than that of MOS transistors. The drawback is that it consumes a lot of power.

[0004] Therefore, by forming a composite circuit of MOS transistors and bipolar transistors, the drawbacks of each can be compensated for and the advantages of each can be utilized.

An example of this bipolar MOS composite device structure is the IEEE Transaction on El
ectron Devices, Vol. ED-16,
No. 11, 1969, P. 946. However, since one bipolar transistor is a vertical bipolar transistor with an N-type substrate as its collector, its collector resistance is high and its performance is not high. Furthermore, since the other bipolar transistor is a lateral type, it has a large parasitic capacitance and similarly does not have high performance. Therefore, even if a bipolar MOS composite circuit is constructed using these bipolar devices, a high-speed circuit cannot be obtained. Further, another example of a bipolar MOS composite device structure is published in Japanese Patent Laid-Open No. 100461/1983. It is a vertical bipolar transistor separated from the P-type substrate, but in the PMOS part, the base and PM
The OS drains are overlapping. Furthermore, in the NMOS section, the base also serves as the P well of the NMOS. Therefore, using these devices, bipolar MOS
If a composite circuit is constructed, a latch-up phenomenon will occur in the PMOS section, and even if it does not occur, in the NMOS section, the capacitance between the base and collector of the bipolar transistor is large, making it impossible to obtain a high-speed circuit.

[0006]

As described above, with the conventional bipolar MOS composite device structure, it has not been possible to obtain a high-speed, highly reliable bipolar MOS composite circuit.

An object of the present invention is to provide a device structure capable of realizing a high-speed, highly reliable bipolar MOS composite circuit.

[0008] Furthermore, an example of the layout of a bipolar MOS composite inverter is the IEEE Transac-tio
n on Electron Devices, Vol.
．． ED-16, No. 11, 1969, P. 946. However, since this layout example is a circuit layout without a bipolar transistor extraction element, it has the disadvantage that power consumption is large and it is not practical.

Another object of the present invention is to provide a layout method for a high-density bipolar MOS composite circuit with low power consumption, including extraction elements of bipolar transistors.

Another object of the present invention is to
S LSI, bipolar LSI, and bipolar MO
The object of the present invention is to provide a bipolar MOS composite LSI that is high speed, low power consumption, high density, and highly reliable by compensating for the drawbacks of S composite devices.

[0011]

[Means for Solving the Problems] In order to achieve the above object, the output stage is configured with bipolar transistors, and MOS
In a BiMOS device that forms a bipolar MOS composite circuit that uses transistors for logic and constitutes a circuit that drives bipolar transistors, the bipolar transistor is a vertical type separated from a P-type substrate, and the base region is connected to the drain and source regions of the MOS. It is separated from The vertical type refers to a type in which the essential operating parts of the emitter, base, and collector are arranged vertically.

[0012] Furthermore, BiMOS forms a bipolar MOS composite circuit in which an output stage is formed by a bipolar transistor, a circuit for taking logic and driving the bipolar transistor is formed by a MOS transistor, and a charge extracting means is provided at the base of the bipolar transistor. In the device, a bipolar transistor with its collector connected to a first potential and its emitter connected to an output terminal is connected to P
P formed in a first region separated from the type substrate and connected between the base and collector of the bipolar transistor.
The MOS transistor is formed in a second region separated from the P-type substrate, and the base charge extraction means connected to the base of the bipolar transistor is separated from the base region of the bipolar transistor.

[0013] Furthermore, a totem-pole output stage is formed by the first bipolar transistor in the upper stage and the second bipolar transistor in the lower stage, and the first field effect transistor and the second field effect transistor are connected between the base and collector of the first bipolar transistor. A CMOS transistor of a second field effect transistor between the base and collector of the bipolar transistor constitutes a circuit that takes logic and drives the bipolar transistor, and a first charge extraction means connected to the base of the first bipolar transistor. B forming a bipolar CMOS composite circuit with second charge extraction means connected to the base of the second bipolar transistor;
In the iMOS device, the distance between the first bipolar transistor and the first field effect transistor is shorter than the distance between the first bipolar transistor and the second field effect transistor; The distance to the transistor is shorter than the distance between the second bipolar transistor and the first field effect transistor, and the distance between the first bipolar transistor and the first charge extraction means is shorter than the distance between the first bipolar transistor and the second field effect transistor. The distance between the second bipolar transistor and the second charge extraction means is shorter than the distance between the second bipolar transistor and the first charge extraction means.

[0014]

[Operation] The output stage is composed of bipolar transistors, and M
In a BiMOS device that forms a bipolar MOS composite circuit that uses OS transistors for logic and also constitutes a circuit that drives bipolar transistors, the bipolar transistor is a vertical type separated from a P-type substrate.
By separating the base region from the drain and source regions of the MOS, the bipolar transistor is a vertical type separated from the P-type substrate, so a high performance bipolar transistor is obtained and high-speed circuit operation is possible. Also,
Since the base region of the bipolar transistor is separated from the drain and source regions of the MOS, measures against the latch-up phenomenon are facilitated. Therefore, a bipolar MOS composite LSI with high speed, low power consumption, and high reliability can be obtained. In addition, the output stage is configured with bipolar transistors,
In a BiMOS device that forms a bipolar MOS composite circuit in which MOS transistors provide logic and drive a bipolar transistor, and a charge extraction means is provided at the base of the bipolar transistor, the collector is connected to a first potential, and the emitter A bipolar transistor connected to the output terminal is formed in a first region separated from the P-type substrate, and a PMOS transistor connected between the base and collector of the bipolar transistor is formed in a first region separated from the P-type substrate. By separating the charge extraction means from the base region of the bipolar transistor, which is formed in the region No. 2 and connected to the base of the bipolar transistor, a high-performance bipolar transistor can be obtained and high-speed circuit operation is possible. Become. In addition, the bipolar transistor area and the PMO
Since the area is divided into S areas, it becomes easy to take measures against the latch-up phenomenon. Further, since a charge extraction means is provided at the base of the bipolar transistor and the charge extraction means is separated from the base region of the bipolar transistor, a circuit with low power consumption characteristics can be obtained without a latch-up phenomenon. Therefore, a bipolar MOS composite LSI with high speed, low power consumption, and high reliability can be obtained.

[0015] Furthermore, a totem pole output stage is formed by the first bipolar transistor in the upper stage and the second bipolar transistor in the lower stage, and the first field effect transistor and the second field effect transistor are connected between the base and collector of the first bipolar transistor. A CMOS transistor of a second field effect transistor between the base and collector of the bipolar transistor constitutes a circuit that takes logic and drives the bipolar transistor, and a first charge extraction means connected to the base of the first bipolar transistor. B forming a bipolar CMOS composite circuit with second charge extraction means connected to the base of the second bipolar transistor;
In the iMOS device, the distance between the first bipolar transistor and the first field effect transistor is shorter than the distance between the first bipolar transistor and the second field effect transistor; The distance to the transistor is shorter than the distance between the second bipolar transistor and the first field effect transistor, and the distance between the first bipolar transistor and the first charge extraction means is shorter than the distance between the first bipolar transistor and the second field effect transistor. By making the distance between the second bipolar transistor and the second charge extraction means shorter than the distance between the second bipolar transistor and the first charge extraction means, the bipolar CMOS Composite circuits can be mounted on semiconductor substrates with high density. Therefore, a bipolar MOS composite LSI with high speed, low power consumption, and high density can be obtained.

[0016]

EXAMPLES The present invention will now be explained in detail by way of examples.

FIG. 2 shows a totem pole output type 2-input NAN.
A circuit D is shown.

In FIG. 2, 20 is a first NPN transistor (hereinafter abbreviated as NPN) whose collector is connected to the power supply terminal 203 and its emitter is connected to the output terminal 202; 21 is a first NPN transistor whose collector is connected to the output terminal 202; Emitter is at ground potential G
A second NPN connected to a fixed potential terminal which is ND, 2
01 is two input terminals, 22 and 23 are PMOSs in which each gate is connected to a different input terminal 201, and each source and each drain are connected in parallel between the collector and base of the first NPN 20; 26 and 27 are NMOSs in which each gate is connected to a different input terminal 201, and each drain and each source are connected in series between the collector and base of the second NPN 21; This is a resistor provided between the base and emitter of the NPNs 20 and 21 of No. 2.

FIG. 8 shows the logical operation of this circuit.

First, when either input 201 is at the "0" level, either PMOS 22 or 23 is turned on, and N
Either MOS 26 or 27 is turned off. Therefore, the base potential of the first NPN 20 rises, and the first NPN
20 is turned on, and the base and emitter of the second NPN 21 are short-circuited through the resistor 211, and the first NPN 21 is turned off.
The emitter current of the NPN 20 charges the load and the output 202
is at the “1” level.

When both inputs 201 are at “0” level, P
Both MOS22 and 23 are turned on, and NMOS26,
27 are both turned off. Therefore, the operation is the same as above and the output 202 becomes "1".

On the other hand, when both inputs 201 are at the "1" level, both PMOS22 and 23 are turned off, and NMOS2
Both 6 and 27 are turned on. Therefore the first NPN
20 is turned off because its base and emitter are short-circuited via a resistor 210, and the base and collector of the second NPN 21 are short-circuited via NMOS 26 and 27, so that current flows from the output 202 to the base of the second NPN 21. is supplied, the second NPN 21 is turned on, and the output 202 is “0”
level. Resistors 210 and 211 shunt the base current when the NPN transistor is turned on;
It functions to extract the accumulated charge when the N transistor is turned off.

According to this circuit, a two-input NAND circuit can be realized with a minimum configuration of CMOS and bipolar transistors. In addition, according to this circuit, the N
Since a PN bipolar transistor is used, ultra high-speed operation is possible.

Further, according to the present circuit, a high input impedance, low output impedance circuit can be realized, and the power supply 20
Since a conductive bus is not created between 3 and ground, low power consumption characteristics can be achieved.

[0025] Here, the portion consisting of the NMOSs 26 and 27, the bipolar transistor 21, and the resistor 211 can be regarded as a pull-down circuit in the logic circuit.

FIG. 3 shows a layout pattern that can suitably configure this bipolar MOS composite circuit, and FIG. 1 shows a vertical structure for easier understanding. Although FIG. 1 shows an inverter circuit, common concepts are represented by the same symbols as in FIG.

In FIG. 3, the pattern of the buried layer 227 in FIG. 1 is omitted for the sake of brevity. PMOS 22, 23, NPN 20, resistors 210, 21 in isolation 212
1 and NMOS 26 and 27, and an NPN 21 is configured in the isolation 213. Gate electrode 2 in Figure 3
20 and 221 show the numbers of the MOS transistors corresponding to those in FIG. P+ region 219 and gate electrode 220,
PMOS22, 23 are configured from 221, and P-well 2
N+ region 223 in 14 and gate electrodes 221, 220
NMOSs 26 and 27 are constructed from the above. NPN20 is P
The region 217 is the base, the N+ region 218 in the P region 217 is the emitter, and the N+ region 215 is the collector. Resistors 210 and 211 are constructed from P regions 216 and 222, respectively. The NPN 21 is based on the P region 225 in the isolation 213, and is based on the NPN in the P region 225.
The + region 226 is used as an emitter, and the N+ region 224 is used as a collector.

Next, the connections between each element will be explained. N
The collector 215 of the PN 20 and the sources of the PMOS 22 and 23 are connected to the power supply by the AL wiring 42. × mark is A
The contact between the L wiring and each element is shown. PMOS22,
The drain of NPN 23, the base of NPN 20, and one end of resistor 210 are connected to each other by AL wiring 228. resistance 21
The other end of the NPN 20 and the emitter 218 of the NPN 20 are connected by an AL wiring 228. Emitter 22 of NPN21
6, one end of the resistor 211, and the P well 214 are connected to the AL wiring 43.
connected to ground potential by The other end of the resistor 211, the source of the NMOS 27, and the base of the NPN 21 are connected by AL wiring 230, respectively. The drain of the NMOS 26 and the collector 224 of the NPN 21 are connected by an AL wiring 231. Although not shown, the emitter 218 of the NPN 20 and the collector 224 of the NPN 21 are connected by a second-layer AL wiring.

From the layout pattern shown in FIG.
Figure 4 shows the pattern excluding wiring and contacts. That is, if the pattern in FIG. 4 is contacted with the AL wiring shown in FIG. 3, a 2-input NAND circuit can be obtained, and if it is contacted with other AL wiring, an inverter or a 2-input NOR circuit can be constructed. Furthermore, when configuring a flip-flop or the like, the required number of patterns shown in FIG. 4 may be used by arranging them horizontally. Therefore, if FIG. 4 is used as a basic cell, bipolar MO
It is possible to configure an S complex LSI.

In this embodiment, the bipolar transistors 20 and 21 constituting the bipolar MOS composite circuit are of vertical type separated from the P-type substrate, so that high-performance bipolar transistors are obtained and high-speed circuit operation is possible. Further, since the base regions 217 and 225 are separated from the drain and source regions 219 and 223 of the MOS, measures against the latch-up phenomenon are facilitated.

Furthermore, bipolar transistors 20 and 21 constituting a bipolar MOS composite circuit are formed in regions 212 and 213 separated from the P-type substrate, and the PMOS 22 and
23 is formed in a region 212 separated from the P-type substrate,
A resistor 210 (area 216
) is separated from the base region 217, resulting in a bipolar MOS composite LS with high speed, low power consumption, and high reliability.
You can get I.

Further, the distance between the first bipolar transistor 20 and the first field effect transistors 22 and 23 constituting the bipolar MOS composite circuit is the same as that between the first bipolar transistor 20 and the second field effect transistors 26 and 23.
7, the second bipolar transistor 2
The distance between the first bipolar transistor 20 and the second field effect transistor 26, 27 is shorter than the distance between the second bipolar transistor 21 and the first field effect transistor 22, 23, and the distance between the first bipolar transistor 20 and the first charge extraction Means 21
0 is shorter than the distance between the first bipolar transistor 20 and the second charge extraction means 211, and the distance between the second bipolar transistor 21 and the second charge extraction means 211 is shorter than the distance between the second bipolar transistor 20 and the second charge extraction means 211. 21
Since the distance between the first charge extracting means 210 and the first charge extracting means 210 is shorter than the distance between the first charge extracting means 210 and the first charge extracting means 210, the bipolar MOS composite circuit can be efficiently and densely mounted on the semiconductor substrate. Therefore, according to this embodiment, a bipolar MOS composite LSI with high speed, low power consumption, high density, and high reliability can be realized.

FIG. 5 shows a totem pole output type 2-input NAN.
Another circuit of the D circuit is shown. Resistor 2 in the embodiment of FIG.
10 to NMOS240 and PMOS242, resistor 211
This is a circuit in which NMOS241 is replaced with NMOS241. NMOS
The gate of 240 is connected to the power supply terminal 203, and the train and source are connected to the base and emitter of NPN 20, respectively. The gate of NMOS241 is connected to the power supply terminal 203,
The drain and source are connected to the base and emitter of NPN 21, respectively. The gate of PMOS 242 is connected to ground potential, and the drain and source are connected to the emitter and base of NPN 20, respectively. Components that are the same as in FIG. 2 are designated by the same numbers. The operation is almost the same as in FIG. NMOS241
always operates in the non-saturation region and serves as a substitute for the resistor 211. PMOS242 has either input 201 set to “0”.
When the output 202 is at the "0" level, it works to raise the output 202 to the power supply voltage, and when the output 202 is at the "0" level, the NMOS 240 short-circuits the base and emitter of the NPN 20, and the NPN
20 is turned off, eliminating through current and reducing power consumption. According to this circuit, since a MOS transistor having a small channel width is used instead of a resistor, the degree of integration can be further improved.

[0034] Here, the portion consisting of the NMOSs 26 and 27, the bipolar transistor 21, and the NMOS 241 can be regarded as a pull-down circuit in the logic circuit.

FIG. 6 shows a layout pattern that can suitably configure this bipolar MOS composite circuit. In FIG. 6, the pattern of the embedded layer and the like are omitted for the sake of brevity. PMOS22, 23, 242, NP in isolation 243
N20 and NMOS26, 27, 240, 241 are configured, and NPN21 is configured in isolation 244. 5 on the gate electrodes 253, 254, 255, 256
The number of the MOS transistor corresponding to is shown. PM from P+ region 249 and gate electrodes 253, 254, 255
OS 242, 23, 22 are configured, and N+ region 250 in P well 245 and gate electrodes 254, 255 are
MOSs 26 and 27 are configured. Also, P-well 245
NMOSs 240 and 241 are constructed from N+ regions 251 and 252 and gate electrodes 256 inside. NPN20 is P
The region 247 is the base, the N+ region 248 in the P region 247 is the emitter, and the N+ region 246 is the collector. NPN21 is P region 2 in isolation 244
58 as a base, N+ region 259 within P region 258
is used as an emitter, and the N+ region 257 is used as a collector.

Next, the connections between each element will be explained. N
The collector 246 of the PN 20, the sources of the PMOSs 22 and 23, and the gates 256 of the NMOSs 240 and 241 are connected to the power supply by the AL wiring 42. In the figure, the x marks indicate contacts between the AL wiring and each element. Drains of PMOS22 and 23, base 247 of NPN20 and PMOS242
The sources of are connected to each other by AL wiring 260. N
The emitter 248 of PN20 and the drain of PMOS242 are connected by AL wiring 261. PMOS24
2 drain and NMOS26 drain and NMOS2
40 sources are connected by an AL wiring 262. NMOS26 drain and NPN21 collector 257
are connected by an AL wiring 263. The source of the NMOS 27, the drain of the NMOS 241, and the base 258 of the NPN 21 are connected to each other by an AL wiring 264. Emitter 259 of NPN21, source of NMOS241, gate 253 of PMOS242 and P well 245
is connected to the ground potential by the AL wiring 43.

From the layout pattern shown in FIG.
FIG. 7 shows the pattern excluding wiring and contacts. In other words, if the pattern in FIG. 7 is contacted with the AL wiring shown in FIG. 6, a 2-input NAND circuit can be formed, and if it is contacted with other AL wiring, an inverter or a 2-input NOR circuit can be configured. Furthermore, when configuring a flip-flop or the like, the required number of patterns shown in FIG. 7 may be used by arranging them horizontally. Therefore, if FIG. 7 is used as a basic cell, bipolar M
An OS composite LSI can be configured.

In this embodiment, since the bipolar transistors 20 and 21 constituting the bipolar MOS composite circuit are of vertical type separated from the P-type substrate, high-performance bipolar transistors are obtained and high-speed circuit operation is possible. Furthermore, since the base regions 247 and 258 are separated from the drain and source regions 249 and 250 of the MOS, measures against the latch-up phenomenon are facilitated.

Further, bipolar transistors 20 and 21 constituting a bipolar MOS composite circuit are formed in regions 243 and 433 separated from the P-type substrate, and PMOS 22 and
23 is formed in a region 243 separated from the P-type substrate,
NMOS240, PMO which is base charge extraction means
Since S242 is separated from the base region 247, a bipolar MOS composite LSI with high speed, low power consumption, and high reliability can be obtained.

Furthermore, the distance between the first bipolar transistor 20 and the first field effect transistors 22 and 23 constituting the bipolar MOS composite circuit is the same as that between the first bipolar transistor 20 and the second field effect transistors 26 and 23.
7, the second bipolar transistor 2
The distance between the first bipolar transistor 20 and the second field effect transistor 26, 27 is shorter than the distance between the second bipolar transistor 21 and the first field effect transistor 22, 23, and the distance between the first bipolar transistor 20 and the first charge extraction Means 24
0,242 is shorter than the distance between the first bipolar transistor 20 and the second charge extraction means 241, and the distance between the second bipolar transistor 21 and the second charge extraction means 241 is shorter than the distance between the second bipolar transistor 20 and the second charge extraction means 241. Since the distance is shorter than the distance between the bipolar transistor 21 and the first charge extraction means 240, 242, the bipolar MOS composite circuit can be efficiently and densely mounted on the semiconductor substrate. Therefore, according to this embodiment, high speed, low power consumption, high density,
A highly reliable bipolar MOS composite LSI can be realized.

[0041]

According to the present invention, a vertical bipolar transistor separated from a substrate is used, and the base region is formed into a MOS transistor.
Since the bipolar MOS composite circuit is constructed by separating the source and drain regions of the circuit, a high speed, low power consumption, and highly reliable bipolar MOS composite LSI can be realized.

According to the present invention, the bipolar transistor is formed in a region separated from the substrate, the PMOS is formed in a region separated from the substrate, and the base charge extracting means is separated from the base region to form a bipolar MOS composite circuit. As a result, a bipolar MOS composite LSI with high speed, low power consumption, and high reliability can be obtained.

Further, according to the present invention, bipolar MOS
The devices that make up the composite circuit are mounted in an optimal arrangement, resulting in a high-speed, low-power, high-density bipolar MO
S-complex LSI can be realized.

[Brief explanation of the drawing]

FIG. 1 is a vertical structure diagram of a device according to an embodiment of the present invention.

FIG. 2 is a bipolar CMOS composite two-input NAND circuit diagram.

FIG. 3 is a pattern diagram configuring the circuit of FIG. 2 with basic cells showing one embodiment of the present invention.

FIG. 4 is a basic cell showing an embodiment of the present invention.

FIG. 5 is a bipolar CMOS composite two-input NAND circuit diagram.

FIG. 6 is a pattern diagram configuring the circuit of FIG. 5 with basic cells showing an embodiment of the present invention.

FIG. 7 is a basic cell showing an embodiment of the present invention.

FIG. 8 is a logical operation of a circuit showing one embodiment of the present invention.

[Explanation of symbols]

20, 21...NPN transistor, 22, 23, 242
...PMOS transistor, 26, 27, 240, 241
...NMOS transistor, 217, 225...Base region, 219, 223...MOS source, drain region, 2
12,213...N well region (isolation), 2
16, 222...P region (resistors 210, 211).

Claims (6)

[Claims] Claim 1: In a BiFET device that forms a bipolar FET composite circuit that includes a bipolar transistor to configure an output stage, takes logic using a field effect transistor (FET), and configures a circuit that drives the bipolar transistor, the bipolar transistor is A semiconductor integrated circuit device characterized in that it is a vertical type separated from a substrate, and a base region is separated from a drain and source region of an FET. 2. The semiconductor integrated circuit device according to claim 1, wherein the bipolar transistor is an NPN bipolar transistor, the substrate is a P-type substrate, and the FET is a MOS transistor. 3. A bipolar FET composite comprising a bipolar transistor to form an output, a field effect transistor (FET) to perform logic and a circuit for driving the bipolar transistor, and a charge extraction means provided at the base of the bipolar transistor. BiFE forming the circuit
In the T device, a bipolar transistor whose collector is connected to a first potential and whose emitter is connected to an output terminal is formed in a first region separated from the substrate, and the bipolar transistor is connected between the base and collector of the bipolar transistor. A semiconductor integrated circuit device characterized in that the FET is formed in a second region separated from the substrate, and the base charge extracting means connected to the base of the bipolar transistor is separated from the base region of the bipolar transistor. . 4. A semiconductor integrated circuit device according to claim 3, wherein the bipolar transistor is an NPN bipolar transistor, the substrate is a P-type substrate, and the FET is a MOS transistor. 5. A totem pole output stage is configured by the first bipolar transistor and a second bipolar transistor in the lower stage, and a first field effect transistor (FET) is formed between the base and collector of the first bipolar transistor.
and a complementary FET (CFE) of the second field effect transistor between the base and collector of the second bipolar transistor.
A first charge extraction means connected to the base of the first bipolar transistor and a second charge connected to the base of the second bipolar transistor constitute a circuit that takes logic and drives the bipolar transistor in T). In a BiFET device forming a bipolar CFET composite circuit provided with extraction means, the distance between the first bipolar transistor and the first field effect transistor is shorter than the distance between the first bipolar transistor and the second field effect transistor. , the distance between the second bipolar transistor and the second field effect transistor is shorter than the distance between the second bipolar transistor and the first field effect transistor, and the distance between the first bipolar transistor and the first charge extraction means is The distance is shorter than the distance between the first bipolar transistor and the second charge extraction means, and the distance between the second bipolar transistor and the second charge extraction means is shorter than the distance between the second bipolar transistor and the first charge extraction means.
A semiconductor integrated circuit device characterized in that the distance between the device and the charge extracting means is shorter than that of the device. 6. In claim 5, the bipolar transistor is an NPN bipolar transistor, and the FET is a MOS transistor.
A semiconductor integrated circuit device characterized by being a transistor.