JPH0563944B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a master slice type semiconductor integrated circuit that utilizes a multilayer metal wiring structure.

[Technical background of the invention and its problems]

In a master slice type semiconductor integrated circuit, a master chip is formed by forming a plurality of cell rows, which are a collection of basic cells made up of multiple elements, on a semiconductor substrate, and metal wiring is applied to this to create the desired logic. It is something that realizes a function.

By conventional general master slicing method
In a CMOS integrated circuit, a first layer metal wiring and a second layer metal wiring are used to realize circuit functions within each basic cell. Then, a wiring area is provided between the cell rows, terminals are led out from both ends of each basic cell to this wiring area, and first-layer metal wiring and second-layer metal wiring are applied to the wiring area as well. connection is being made.

In such a conventional structure, since a wiring area is provided between the cell rows, there is a problem in that the chip utilization rate is low.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a master slice type semiconductor integrated circuit which is capable of improving the chip utilization rate and increasing the degree of freedom in wiring between cells.

[Summary of the invention]

In the present invention, basic cells are densely arranged in a symmetrical pattern without providing a wiring area between adjacent cell columns. The symmetrical pattern is a pattern in which the conductivity types of elements constituting basic cells in adjacent cell rows are symmetrical, and may be linearly symmetrical or rotationally symmetrical. The circuit function of each basic cell is the first
This is realized only by layered metal wiring, and the power supply line (including the ground line) is shared by adjacent cell columns, and is formed by first layer metal wiring on the boundary between the cell columns. Therefore, connections between cells are made on the cell column area using second or third layer metal wiring, but in this case,
It is desirable that the contact positions between these wiring lines and the terminals of each basic cell are distributed and arranged so that they are not lined up in a straight line on each basic cell region.

〔Effect of the invention〕

According to the present invention, since inter-cell connections are made on the cell column area without providing a special wiring area between the cell columns,
Improves chip utilization. Moreover, since the power supply line and the intra-cell wiring are composed of only the first layer metal wiring, and the contact positions between the basic cell terminal and the second and third layer metal wiring are distributed over the basic cell area,
High degree of freedom in wiring. Therefore, complex logic integrated circuits can be easily realized.

[Embodiments of the invention]

An example in which the present invention is applied to a CMOS integrated circuit will be described below. FIG. 1 shows a pattern of one basic cell portion, which includes the first layer metal wiring, and FIG. 2 shows an equivalent circuit of the basic cell in this state. In FIG. 1, 11 is a region of p-channel MOSFET-Q _p1 and Q _p2 , and 12 is a region of p-channel MOSFET-Q _p3 and Q _p4 . 13 is a p-well, within which there is an n-channel.
A region 14 for MOSFETs Q _o1 and Q _o2 and a region 15 for n-channel MOSFETs Q _o3 and Q _o4 are provided. Q _p1 , Q _o1 , Q _p2 , Q _o2 , Q _p3 , Q _o3 and
Each FET pair Q _p4 , Q _o4 has a common polycrystalline silicon gate electrode. The hatched portions 16 ₁ to 16 ₄ in FIG. 1 are the first layer metal wiring;
6 ₁ is a V _DD line, 16 ₂ is a V _SS line, and 16 ₃ and 16 ₄ are intra-cell wiring lines. These first layer metal interconnections 16 ₁
By applying ~ ₁₆₄ , as shown in Figure 2,
The circuit function of this basic cell is realized. Further, 17a to 17e are the first layer metal wirings 16 ₁ to 1
This is a contact hole for connecting a basic cell coated with 6 ₄ to other basic cells through second and third layer metal wiring. Contact hall 17a~
17d correspond to the input terminals A to D in FIG. 2, and the contact hole 17e corresponds to the output terminal E.
corresponds to

FIG. 3 schematically shows a cell column pattern of such basic cells. That is, cell rows 18, 18 ₁ ,
18 ₂ ... is a symmetrical pattern with adjacent ones,
Adjacent V _DD lines 16 ₁ , 16 ₁₁ , 16 ₁₂ ,
. . . and V _SS lines 16 ₂ , 16 ₂₁ , 16 ₂₂ , . . . are shared and densely arranged.

According to this embodiment, the cell rows are densely arranged without any special wiring area between them, and the power supply lines are shared between adjacent cell rows, which improves the chip utilization rate through high-density integration. is planned. In addition, the power supply line and all intra-cell wiring are constructed from first-layer metal wiring, and inter-cell connections are made using second-layer or higher-layer metal wiring on the cell area, so the layout of inter-cell connection wiring is easy. . Moreover, in this case, since the contact hole positions of the metal wiring in the second layer or higher are distributed over the cell region, the degree of freedom in wiring is high. That is, the second and third layer metal interconnections are usually designed using a CAD system, and many of the interconnections run parallel to the cell columns. For example, in the pattern shown in Figure 1, the generally preferred locations for contact holes are the p-channel MOSFET region far from the power supply lines running on both sides of the cell, and the n-channel MOSFET region far from the power supply lines running on both sides of the cell.
It is on the boundary area with the channel MOSFET area.
However, if the contact holes are arranged in a straight line in this region, the second and third layers parallel to the cell rows
There are significant restrictions on connecting to lower layer terminals through contact holes without bending layer wiring. In this embodiment, since the contact hole positions are dispersed, there are few such restrictions.

The present invention is not limited to the above embodiments. For example, the basic cell is a CMOS structure other than the CMOS structure shown in the example.
structure, or p-channel MOS or n-channel
It may have a MOS structure or may use a bipolar transistor.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the pattern of the basic cell portion with the first layer metal wiring applied according to an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the basic cell in that state, and Fig. 3 is It is a figure showing a cell row pattern using the same basic cell. 16 ₁ to 16 ₄ ...first layer metal wiring, 16 ₁ , 16
₁₁ , 16 ₁₂ , ... V _DD line, 16 ₂ , 16 ₂₁ , 16
₂₂ ,...V _SS line, 17a to 17e...contact hole, ₁₈ , 181, ₁₈₂ ,...cell row.

Claims (1)

[Claims] 1. A plurality of cell rows each having a plurality of basic cells formed by connecting a plurality of elements are formed on a semiconductor substrate, and a desired logic function is achieved by applying multilayer metal wiring. In the semiconductor integrated circuit that will be realized, the conductivity types of the elements that make up the basic cells will be arranged closely so that they are symmetrical in adjacent cell rows, and the connections of the elements that make up each basic cell will be realized using only the first layer metal wiring. At the same time, the power supply line is shared by adjacent cell columns and arranged by first layer metal wiring on the boundary between the cell columns, and the connection between each of the basic cells is made by second or third layer metal wiring. A semiconductor integrated circuit characterized by: