JPH0644613B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a master slice type semiconductor device composed of a plurality of function blocks having a gate array.

[Conventional technology]

Generally, in a master slice type semiconductor device, a plurality of function blocks arbitrarily combined are arranged on a chip, and the function blocks are interconnected to form a desired semiconductor device. And
In this type of semiconductor device, not only wiring for connecting the elements inside each function block but also wiring for connecting each function block is constructed, but conventionally, The wiring in the function block and the wiring between the function blocks are formed by the same two-layer aluminum wiring.

[Problems to be solved by the invention]

In the conventional semiconductor device described above, the function block and the function block are connected by the same two-layer aluminum wiring. Therefore, in order to avoid interference with these internal wiring and mutual wiring, both wirings are separated in the plane direction. Need to be installed. Therefore, the inter-function block wiring must be arranged so as to bypass the function block with respect to the wiring in the function block that is preferentially arranged, which is an obstacle to high integration of the semiconductor device. .

Further, when the two-layer aluminum wiring is used for the internal wiring and the mutual wiring, it is necessary to reduce the wiring width of the aluminum wiring particularly in the internal wiring that requires high integration, and thus the problem of wiring disconnection due to migration easily occurs. Further, when the aluminum wiring is connected to the silicon layer via the minute contact hole, there is a problem that the contact resistance is increased or the contact is opened due to the recrystallized silicon after the aluminum alloy heat treatment.

[Means for solving problems]

In the semiconductor device of the present invention, in order to solve the problems of migration and contact in the wiring and the detour wiring described above and to achieve high integration and reliability improvement, the function block in the semiconductor device has a two-layer high melting point. The wiring structure is such that the function blocks are connected by metal wiring and the function blocks are connected by double-layer aluminum wiring.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and particularly a diagram schematically showing a wiring pattern.

As shown in the figure, this semiconductor device has a configuration in which a plurality of function blocks 2a to 2h are arranged on a chip 1, and the function blocks 2a to 2h are interconnected with each other by inter-wirings 5 and 6 formed in two layers. Connected. Also,
Each of the function blocks 2a to 2h is connected to a large number of circuit elements (not shown) having a gate array structure formed in the function block by two-layered internal wirings 3 and 4, as represented by the function block 2a. ing.

The internal wirings 3 and 4 are composed of a lower first refractory metal wiring 3 and an upper second refractory metal wiring 4, and the circuit element, the first and the first through holes 8 and 8 through the contact hole 7 and the first through hole 8. The two refractory metal wirings 3 and 4 are connected to each other to form a circuit so as to exert a desired function.

The inter-wirings 5 and 6 are composed of a lower first aluminum wiring 5 and an upper second aluminum wiring 6, and the two aluminum wirings 5 and 6 are mutually connected through a second through hole 9 and a third through hole 10. Or the internal wirings 3 and 4 and the like, and the function blocks 2a to 2h are interconnected to provide a semiconductor device chip 1 having a required function and characteristic
Are configured.

According to this configuration, each of the function blocks 2a-2
Since the internal wirings 3 and 4 of h and the mutual wirings 5 and 6 that connect the function blocks to each other have different two-layer wiring structures, even if they overlap each other in a plane pattern, No interference will occur. For this reason, it is possible to freely arrange the respective wirings, and in particular, it is unnecessary to bypass the wirings of the mutual wirings 5 and 6, thereby shortening the wiring length and reducing the layout space, and thus the semiconductor device High integration can be achieved.

Further, since the wirings 3 and 4 in the function block are each made of a refractory metal wiring, even if the wiring width is miniaturized, migration resistance is enhanced and fine wiring can be realized. Furthermore, problems such as contact resistance in the minute contact holes can be solved.

Needless to say, various materials such as molybdenum and tungsten that are currently in practical use can be applied to the refractory metal wiring.

〔The invention's effect〕

As described above, the present invention connects the inside of the function block in the semiconductor device with the two-layer refractory metal wiring,
Because the wiring structure is such that the function blocks are connected by double-layer aluminum wiring, migration resistance can be improved while suppressing an increase in the delay time of the wiring in the function blocks, and the wiring resistance between the function blocks can be improved. Since the delay of the signal transmission time can be reduced while suppressing the deterioration of the migration property, the internal wiring can be miniaturized to achieve high integration and improve the reliability of the connection. By eliminating the detour, the wiring can be shortened and the degree of integration thereof can be improved, so that high integration of the semiconductor device can be achieved.

[Brief description of drawings]

The drawing is a plan view schematically showing a wiring pattern according to an embodiment of the present invention. 1 ... Semiconductor device chip, 2a to 2h ... Function block, 3, 4 ... Internal wiring (3 ... First refractory metal wiring, 4 ... Second refractory metal wiring), 5, 6 ... Mutual Inter-wiring (5 ... first aluminum wiring, 6 ... second aluminum wiring), 7 ... contact hole, 8 ... first
Through hole, 9 ... Second through hole, 10 ... Third
Through hole.

Claims (2)

[Claims] 1. A master slice type semiconductor device comprising a plurality of function blocks, wherein elements inside the function block are connected by refractory metal wiring having a two-layer structure, and the function blocks have a two-layer structure. A semiconductor device characterized by being connected by the aluminum wiring of. 2. A device according to claim 1, wherein elements inside the function block are connected by first and second refractory metal wirings, and the function blocks are connected by first and second aluminum wirings. The semiconductor device according to item 1.