JPH0620111B2 - Monolithic IC - Google Patents
Monolithic ICInfo
- Publication number
- JPH0620111B2 JPH0620111B2 JP24716587A JP24716587A JPH0620111B2 JP H0620111 B2 JPH0620111 B2 JP H0620111B2 JP 24716587 A JP24716587 A JP 24716587A JP 24716587 A JP24716587 A JP 24716587A JP H0620111 B2 JPH0620111 B2 JP H0620111B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- resistor
- monolithic
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はモノシリックＩＣ内の多結晶シリコン抵抗に関
する。FIELD OF THE INVENTION The present invention relates to polycrystalline silicon resistors in monolithic ICs.
［従来の技術］ 従来、モノシリックＩＣ上に高精度かつ高信頼度の抵抗
体を構成する場合には、高信頼度を得るため総並列抵抗
の面積を広くとるような幅広の抵抗パターンが使用さ
れ、かつ、高精度を得るためにその幅広の抵抗パターン
を２つ以上の並列抵抗パターンに区切り、かつ、周囲に
ダミー抵抗パターンが構成されていた。[Prior Art] Conventionally, in the case of configuring a highly accurate and highly reliable resistor on a monolithic IC, a wide resistance pattern that widens the area of total parallel resistance is used to obtain high reliability. In addition, in order to obtain high precision, the wide resistance pattern is divided into two or more parallel resistance patterns, and a dummy resistance pattern is formed around the parallel resistance patterns.
［発明が解決しようとする問題点］ このように２つ以上の並列抵抗パターンに、区切られて
いるため、単一の抵抗体に比して周辺長が長くなり、そ
の結果対基板間の容量が増大するという欠点がある。す
なわち、抵抗体の周辺の部分には電気力線が集中するの
で、この周辺部分に形成される寄生容量は大きい。従っ
て、周辺長が長くなることはその分寄生容量が大きくな
る。このような周辺部での容量はフリンジング容量と呼
ばれている。かかる容量値の増大は、大電流が流れる低
抵抗体でかつ超高周波で動作するモノシリックＩＣのコ
レクタ負荷抵抗では特に問題となる。[Problems to be Solved by the Invention] Since the two or more parallel resistance patterns are divided as described above, the peripheral length is longer than that of a single resistor, and as a result, the capacitance between the substrate and the substrate is increased. Has the drawback of increasing. That is, since lines of electric force are concentrated on the peripheral portion of the resistor, the parasitic capacitance formed on this peripheral portion is large. Therefore, the longer the peripheral length, the larger the parasitic capacitance. The capacitance in such a peripheral portion is called a fringing capacitance. Such an increase in the capacitance value is particularly problematic in a collector load resistance of a monolithic IC which is a low resistance through which a large current flows and which operates at an ultrahigh frequency.
［問題点を解決するための手段］ 本発明のモノシリックＩＣは、多結晶シリコン抵抗体
が、下層部の多結晶シリコン抵抗体層と、この抵抗体層
に少なくとも一部が重なって設けられた上層部の多結晶
シリコン抵抗体層と、これら下層部および上層部の多結
晶シリコン抵抗体層を並列に接続する配線層とで構成さ
れている。[Means for Solving the Problems] In the monolithic IC of the present invention, a polycrystalline silicon resistor is an upper layer in which a polycrystalline silicon resistor layer in a lower layer portion and at least a part of the polycrystalline silicon resistor layer are overlapped with the resistor layer. Part of the polycrystalline silicon resistor layer, and a wiring layer connecting the lower and upper polycrystalline silicon resistor layers in parallel.
［実施例］ 次に、本発明について図面を参照して説明する。EXAMPLES Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示すモノシリックＩＣ内の
抵抗パターンの平面図である。FIG. 1 is a plan view of a resistance pattern in a monolithic IC showing an embodiment of the present invention.
第１図に示すように、高層側の多結晶シリコン抵抗体１
〜３と、基板により近い低層側の多結晶シリコン抵抗体
４、５と、多結晶シリコン抵抗体１〜５を両端で並列接
続するアルミニウムの配線層１６、１７と、多結晶シリ
コン抵抗体１〜５と配線層１６、１７とを接続するコン
タクト６〜１５とを含む。高層側の多結晶シリコン抵抗
体１〜３と、低層側の多結晶シリコン抵抗体４、５と
は、図示のように、隣合うもの同士それぞれの一部が平
面的にみて互いに重なるように配置されている。As shown in FIG. 1, the polycrystalline silicon resistor 1 on the higher layer side
3 to 3, lower-layer polycrystalline silicon resistors 4 and 5 closer to the substrate, aluminum wiring layers 16 and 17 that connect the polycrystalline silicon resistors 1 to 5 in parallel at both ends, and the polycrystalline silicon resistors 1 to 5. 5 and contacts 6 to 15 connecting the wiring layers 16 and 17. As shown in the figure, the high-layer side polycrystalline silicon resistors 1 to 3 and the low-layer side polycrystalline silicon resistors 4 and 5 are arranged such that some of the adjacent ones overlap each other in plan view. Has been done.
このように形成することにより、上層部の抵抗１、２、
３の周辺部のうち下層部の抵抗体４、５と重なっている
部分からの電気力線は下層部の抵抗体４、５の存在によ
り、対基板との間の寄生容量の形成には寄与せず、この
結果、全体としての対基容量は小さくなる。By forming in this way, the resistors 1, 2,
The lines of electric force from the portion of the peripheral portion of 3 which overlaps with the resistors 4 and 5 in the lower layer contribute to the formation of parasitic capacitance with the substrate due to the presence of the resistors 4 and 5 in the lower layer. As a result, the overall capacity of the base is reduced.
［発明の効果］ 以上説明したように本発明によれば、単一の幅広の抵抗
パターンを分割した場合と比較して、フリンジング容量
が少なくなるので総合の対基板容量を減少できる効果が
ある。[Effects of the Invention] As described above, according to the present invention, since the fringing capacitance is reduced as compared with the case where a single wide resistance pattern is divided, there is an effect that the total capacitance to substrate can be reduced. .
第１図は本発明の一実施例を用いてモノシリックＩＣ内
に形成した抵抗パターンの平面図である。 １〜３……高層側の多結晶シリコン抵抗体、４、５……
低層側の多結晶シリコン抵抗体、６〜１５……コンタク
ト、１６、１７……配線層。FIG. 1 is a plan view of a resistance pattern formed in a monolithic IC using an embodiment of the present invention. 1 to 3 ... Polycrystalline silicon resistors on the higher layer side, 4, 5 ...
Polycrystalline silicon resistor on the lower layer side, 6 to 15 ... Contact, 16, 17 ... Wiring layer.
Claims (1)
シリコン抵抗体層と、この抵抗体層に少なくとも一部が
重なって設けられた上層部の多結晶シリコン抵抗体層
と、これら下層部および上層部の多結晶シリコン抵抗体
層を並列に接続する配線層とでなることを特徴とするモ
ノシリックＩＣ。1. A polycrystal silicon resistor, a polycrystal silicon resistor layer in a lower layer part, a polycrystal silicon resistor layer in an upper layer part at least partially overlapped with the resistor layer, and these lower layers. Monolithic IC, which comprises a wiring layer for connecting the upper and upper polycrystalline silicon resistor layers in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24716587A JPH0620111B2 (en) | 1987-09-29 | 1987-09-29 | Monolithic IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24716587A JPH0620111B2 (en) | 1987-09-29 | 1987-09-29 | Monolithic IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6489357A JPS6489357A (en) | 1989-04-03 |
| JPH0620111B2 true JPH0620111B2 (en) | 1994-03-16 |
Family
ID=17159405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24716587A Expired - Lifetime JPH0620111B2 (en) | 1987-09-29 | 1987-09-29 | Monolithic IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0620111B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2681978B1 (en) * | 1991-09-26 | 1993-12-24 | Sgs Thomson Microelectronics Sa | PRECISION RESISTANCE AND MANUFACTURING METHOD. |
-
1987
- 1987-09-29 JP JP24716587A patent/JPH0620111B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6489357A (en) | 1989-04-03 |
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