JPS59133655A - Address stop control circuit - Google Patents

Abstract

PURPOSE:To attain correctly required data at a required time, by releasing an address holding function when the coincidence between addresses is detected and using this function selectively. CONSTITUTION:An FF 36, where the coincidence between an execution address of a program and an address set from the external is stored, and an FF 37 which indicates that a memory operation is performed at a current time are provided. An NAND gate 38 which inhibits the output of the FF 36 by the output of the FF 37 is provided, and a signal 40 which selects whether the output of the gate 38 is held or not is supplied from the external. An NAND gate 39, to which a comparator 33 outputs the output, and an AND gate 34 which controls supply/inhibition of operating clocks to a program counter/register 31 by outputs of gates 38 and 39 are provided. Thus, the address stop can be set even during the memory operation, and holding or release of the clock supply stop is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a control circuit for address stop used particularly during program debugging.

[Technical background of the invention and its problems]

In hardware/software development, it is an effective method for debugging, etc. to run a program until it reaches a predetermined location or a predetermined state, then temporarily interrupt the operation at that point and check the status of registers, flags, etc. This is a method that has been widely used.

For example, the hardware shown in FIG. 1 is used to execute a program up to a predetermined address and then stop it (address toslag). That is, the address counter/register (
ADRIJ) and the value set in the comparison value register (CADRxz) are compared by the comparator (COMPl, 9), and if a match is detected here, the gate (GZ4) is closed, and therefore the clock generation circuit (CG15) The clock generated by the address counter/register 11 is no longer supplied to the address counter/register 11. This interrupts the operation and has been frequently used in the past as a simple and effective means.

Incidentally, in recent years, processing has become more distributed within processing devices, and for example, the memory section starts operation when the operation start signal (K) is sent from the arithmetic control section (CPU), reads data, etc. When data transfer preparation is completed, CP
It notifies U of this fact and also transfers the data. Therefore, the CPU can perform other processing while the memory section is operating, and can perform efficient operations by taking in and using data from the memory section while taking into consideration the timing.

However, in such a system, if an attempt is made to realize the address stop function, the clock supply to the address counter/register 11 will be immediately stopped when an address match occurs. Therefore, if the data from the memory section is missed and the clock supply is started and the operation is restarted, it is often impossible to continue the operation correctly even if the data is taken in again.

In order to eliminate this drawback, recently, when program control is required such as memory operation, the fact that the addresses match is memorized using a flip-flop, etc., and when program control is no longer necessary, it is memorized once. A method has come to be used in which the output of a previously set flip-flop is enabled and the operation is thereby interrupted. FIG. 2 shows an example of the circuit configuration.

In the figure, the comparator 23 uses the address counter/, the register 21
and the data in the comparison value register 22, and if a match is detected, the flip-flop 26 is turned on and the supply of the operating clock generated by the clock generation circuit 25 is stopped. At this time, if the memory is active and requires program intervention, a flip-flop (F
/F27) is set (memory BUSY), the gate 28 is closed and the stop signal is not transmitted. Therefore, the clock is continuously supplied to the address counter/register 2, and the execution of the program is not interrupted.

When the memory operation is completed, flip-flop 27 is reset. Therefore, the gate 28 is opened, and the presence of the gate 24 stops the supply of the clock generated by the clock generation circuit 25 fl, thus interrupting the execution of one line of the program.

In such a method, although the above-mentioned drawbacks can be solved, even if a match is detected when the flip-flop 27 is set, the flip-flop 26 is only set and the operating clock does not stop, so the program step As the processing progresses, new drawbacks arise, such as data set in registers etc. being destroyed.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks.The present invention has been made in view of the above-mentioned drawbacks.The present invention has been made in view of the above-mentioned drawbacks.The present invention is based on a data processing device having a function of suspending clock supply to an address counter/7 register while a memory device is operating, when an address comparison match is detected. It is an object of the present invention to provide an address/stop control circuit that does not lose necessary data by canceling its hold function and making it selectively usable.

[Summary of the invention]

The present invention is an address/stop control circuit used in a data processing device that has a function of stopping clock supply to an address counter/register 1f during operation of a memory device, and the control circuit is capable of A first flip-flop is provided to store a match between the address and an address set externally, and a second flip-flop is provided to display that the memory is currently operating, and a second flip-flop output is provided. A first gate that inhibits the output of the first flip-flop, a signal that selects whether or not to hold the first gate output is supplied from the outside, and a second gate that controls all comparator outputs. By providing a gate and a third gate that controls supply/inhibition of the operation clock to the program counter/register using the first and second gate outputs, address stop can be set even during memory operation. In addition, it is possible to select whether to suspend or cancel the clock supply, thereby solving the conventional problem when restarting the operation.

This makes it possible to provide a data processing device that can efficiently debug programs.

[Embodiments of the invention]

The present invention will be explained in detail below using FIG.

FIG. 3 is a block diagram showing a one-shot embodiment of the present invention. In the figure, 31 is an address counter/register in which the address at which the program is to be executed is set. 32 is a comparison value register in which a comparison value supplied from the outside (console panel, maintenance panel, etc.) is set. Address counter/register 31 output and register 32 above
The output is provided to comparator 33. The comparator 33 output is fed to a flip-flop 36 where a match is indicated. 37 is a flip-flop that indicates that the memory is in operation (BUSY). The output of the free lag flop 36 and the inverted output of the clip flop 37 are supplied to the Nant gates (G, ?, !l). 39 is Nantes Gate. The above comparator 3 is installed in the Nantes gate 39.
A selection signal is supplied from the outside via the 3 output and a selection signal line (SEL40). Here, the selection signal is gate 3
This signal determines whether or not to hold the 8 output. For details, see below.

35 is an operation clock generation circuit. The operating clock generated here is supplied to the Nant gate (G34) together with the outputs of the Nant gates 38 and 39, and then to the address counter/register 3 and other logic.

The operation of the embodiment of the present invention will be described in detail below.

A feature of the present invention is that a cant gate 39 is inserted. This cant gate 39 comparator 33
This is provided to bypass gate 38 and supply the coincidence signal detected in gate 34 to gate 34.

First, the operation will be explained assuming that the gate 39 does not exist. It is assumed that values have been set in the address counter/register 31 and comparison value register 32 in advance by some means, and that the flip-flops 36 and 37 have been reset.

An operating clock is now generated in clock generation circuit 35, and this operating counter is re-visited to address counter/register 21 via gate 34. By the way, gate 3
4, the condition is satisfied because the freebflops 36 and 37 are each reset (the condition of the gate 38 is not satisfied, so as a result, the gate 34 is established), and the signal is turned on for the address counter/register 3. An operating clock is supplied.

As a result, the value of the address counter/register 31 is updated, and when the comparator 33 detects a match with the value set in the comparison value register 32, the flip-flop 36 is set.

By setting the flip-flop 36, the condition of the gate 38 is satisfied, and as a result, the condition of the gate 34 is not satisfied, the gate 34 is closed, and the supply of the clock is stopped. Therefore, the operation stops. When the operation is restarted, the operation clock is supplied to the address counter/register 31 by resetting the flip-flop 36, and the matching condition is no longer satisfied, so that the operation can be continued.

If the operation progresses further and six operation requests are issued to the memory section,
Flip-flop 37 is cented.

At this point, if the comparator 33 detects a match, the Frisoge flop 36 is set, but since the clip flop 37 is set, the condition of the gate 38 does not hold. As a result, the condition of the gate 34 remains satisfied, so the clock signal is continuously supplied to the address counter/register 3, and the operation does not stop.

By the way, even if there is no match output from the comparator 33, the flip-flop 36 is not reset, and only the match is stored. When the memory operation is completed and the flip-flop 37 is reset, the condition at the gate 38 is satisfied, and as a result, the gate 34 is not established, and the operation is stopped at this point. When starting the operation again, by resetting the flip-flop 36, the memory data has been processed correctly, so the operation can be continued normally.

Next, the operation when the gate 39 is inserted will be explained.

Reference numeral 40 denotes a selection signal line, which determines whether the above-mentioned bypass cocoon function is valid or invalid. When the signal propagating through the selection signal line 40 is a logic "0", the gate 39 is closed and the operation is similar to that described above. Therefore, clip flop 3
When 7 is set, gate 38 is closed, which opens AND gate 34 and provides a clock to 7 address counter/register 31. When the memory operation is completed, the flip-flop 37 is reset, so
Gate 38 is opened, the flip-flop 36 output is transmitted to gate 34, and the clock supply is stopped and operation is interrupted.

In this case, even if a match is detected, the flip-flop 37
If it is set, the process will proceed to the next step, so if you want to interrupt the execution immediately, set the selection signal line 40 to logic "1".
shall be.

When the program is executed in this state, the match signal detected by the comparator 33 will be sent to the gate 39 regardless of the state of the free float block 37 because the gate 39 is open.
4, thereby closing the gate 34 and stopping the clock supply to the address counter/register 31.

Therefore, the operation can be immediately interrupted.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to set an address stop even during a memorization operation, and the program can be continued correctly, thereby providing an effective means for program development, particularly for program debugging in microprogram development. In addition, it is possible to selectively use a function that immediately interrupts the operation when a match occurs, making it possible to obtain the necessary data correctly at the necessary time.

[Brief explanation of drawings]

1 and 2 are block diagrams showing an example of the configuration of a conventional address stop control circuit, and FIG. 3 is a block diagram showing an embodiment of the present invention. 3. Address counter/register (ADH), 3
2... Comparison value register (CADR), 33... Comparator (coMP), 34... AND gate (AG),
35... Clock generation circuit (CG), 36., 37.
... Flip-flop (F/F), 38, 39... NAND game) (NG), 40... Selection signal line (SEL)
.

Claims (1)

[Claims] An address counter in which the program's practical address is sequentially updated and set based on the CLOPAC generated by the clock generation circuit, and a comparator that compares this counter with the value of the register in which the comparison value is set and detects an address match condition. and a first one that stores the coincidence signal that is the output of the comparator.
a second flip-flop that stores that the memory is in operation; and a first gate that inhibits the first flip-flop output when the second flip-flop is set; A signal for selecting whether or not to hold the first gate output is supplied from the outside, and a second gate controls the comparator output using the selection signal, and the first and second gate outputs are used. and a third gate for controlling the supply of clocks to the address counter.