JPS5965306A - Sequence controller - Google Patents

Abstract

PURPOSE:To reduce the load of a master CPU and to improve the efficiency of a sequence controller by providing a slave CPU containing a storage part as well as a master CPU to perform the timer control of an I/O port or a soft flag, etc. CONSTITUTION:For the control of a copying machine, the 1st slave CPU21, the 2nd slave CPU22 and the 3rd slave CPU23 control the input/output of an operation part, an original reader and the input/output of a printer respectively. The CPUs 22 and 23 have four I/O expanders 31-37 and 41-47 respectively. A master CPU11 contains plural sequence control task groups and a real time monitor function which controls said task groups. An interruption is carried out by supplying an interruption signal 53 to the CPU11 from a program interval timer 51. While the interruption signal sent from the CPU21 and a drum clock pulse interruption signal 65 are supplied via a programmable interruption controller 61.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device using a central processing unit (hereinafter referred to as CPU).

Conventionally, when performing 7-can control of a copying machine or the like using a microprocessor sensor, input/output control or management of control information such as flags has been performed using the main mass CPU.

Therefore, in order to keep the output status or flag on for a certain period of time, a timer must be installed in the master CPU.
It was turned off after a certain period of time. However, master C
Because the PU was executing input/output or flags, etc.
When setting a timer for output ports or flags, etc., the time had to be counted by a mask CPU. Therefore, the burden on the master CPU is high,
The problem was that the program was also complicated.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide a sequence control device mV that is easy to program.

In the present invention, the input/output state of a master CPU having a main control function, a slave CPU, and a random access memory (referred to as RAM) of the slave CPU.

It has means for recording the flag state, etc., and means for changing it after the slave CPU receives a timer point command from the master CPU and maintains the finger/foot time in the memorized state, and the mask CPU records the time information t count of the timer. The present invention eliminates the inconvenience of configuring the output boat status and timers for flags and allows the master CPU to set the output boat status and flag type timers without distinction.

According to the device of the present invention configured as described above, timer management such as 10 boats or nft flags can be performed by slay-f CP.
Uc: Master CPU by running independently
! ;f Slave CP asynchronously with timer cent only
The time information of the timer can be counted, reducing the burden on the master CPU and improving efficiency.

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 shows the configuration of a prosensor for realizing the invention. Here, the mask CPU // is, for example, Intel Corporation 1
5, slave CPUs #, 22, and n are CPUs also made by Intel Corporation lf7 Hiro/p. These CPs
U stands for Intel Single Board Computer SBCS
I am using 69. In the embodiment of the present invention, these computers can be used to install, for example, a copying machine.
The first slave cptr 2/ controls the input/output of the operating section, the second slave CPU 22 controls the reader for reading the document, and the third slave CPU 2j controls the input/output of the printer. Both slave CPUs 2J and B have
Each is equipped with a large number of I10 expanders 31S-n and 4t/~17.

The mask CPU 1l has a plurality of sequence control task groups and a real-time monitor function to manage these tasks. The I10 protocol between the master CPU // and each of the slave CPUs 2/, 22, and B is performed using the data bus span 77 (LDBB, ) within each slave CPU. Interrupts are handled by the master CPU/no.5TZ.
5 to 70g interval timer t+tjs3-s)
This is done by Am from si and C which provides the Cronk interrupt signal j3. This interrupt is an interrupt that is counted when 6WAIT of the execution control macro, which will be described later in FIG. 3, is issued. Slave CPU via programmable interlast controller CIr2j9A
The interrupt signal 63 from 2/ and the drum clock pulse interrupt signal 6j are supplied to the master cPUll. slave C
PU,! The interrupt signal 63 from / is generated when a request for data transfer is received from the operation unit (keyboard) 71. The drum clock pulse interrupt signal 6s is a clock interrupt signal that depends on the rotation angle of the photosensitive drum (not shown) of the %1 printer, and is counted when the eJwAIT macro command shown in FIG. 3, which will be described later, is issued. This includes 1j.

This determines the timing of sequence control.

! In addition, the xm = clock interrupt signal 53 from the interval timer 51 is also provided to both slave CPUs 22 N and n. This is the input/output control macro @ TS in Figure 5.
ET is released, both Sleg CPU2J and n
This is an interrupt that is counted by .

The above 10-sensor configuration constitutes a screw-can control device, and its functions can be broadly classified into real-time parallel processing and human output control functions. From now on, it will simply be referred to as a monitor. The PA function of this monitor will be explained below.

This monitor's real-time parallel processing function allows it to set and code the processing programs necessary for each specific application on a task-by-task basis. The multiplicity of task running levels in this monitor corresponds to 1 interrupt level and 1 program level (P level).

There are three states: stopped, stopped, and standby, and all are in the stopped state when the power is turned on. The task is executed using the ENTR macro, and during execution the WAIT macro waits for the completion of an event. In reality, a task can also be put on standby for execution by an interrupt, but in either case, the task is automatically rebd when the cause is removed. Within a P-level task, the above-mentioned real-time parallel processing is possible, and only when one task is stopped or placed on standby.
By checking whether or not there is a task request at number Clllli during the monitor's run tropin scanning, the next requested task is sequentially activated and enters the n execution state.

Figure 2 shows the state transition of tasks. Here, the solid line indicates that each task has an execution control macro LENTLE, S'I'OF
.

It shows the state transition when WAIT, ItVAIT, ESCI) is issued, and the dotted line shows the state transition automatically performed by the monitor. When a task in a stopped state is entered by another task, it becomes executable.

When a running task issues the 5TOP macro, it enters a stopped state, when it issues a WAIT or IWAIT macro, it enters a standby state, and when it issues an (escape) macro, it enters an execution state. When the waiting task becomes a time amplifier, the monitor automatically puts the i5J into the execution state.

Further, a task in an executable state is set to be executed by the monitor's automatic round tropin scanning.

FIG. 3 shows the formant and function of the execution control macro.

When each macro is issued from each task, control is transferred to the monitor by a restart command (R8'l'), and the monitor executes each macro according to its function.

@WAIT is counted by a timer interrupt every - time, and @IWAIT is counted by the i-monitor by an external interrupt at regular intervals (in a non-embodiment, a pulse proportional to the rotation of the drum of the copying machine).

For the input/output system A-like dragon, each point of the input boat, output boat, and knot flag is given an item number (ordinal) for common recognition across both soft and hard concave points, and these are set to off 1, ON), OFF L OFF
) and check (CHECK) person output iii'
JfI! 11 Mataro makes it extremely easy to manage input/output commands or flags using application 10grams.
It is made easy. That is, the monitor receives an input/output control macro command from the application program, and processes the input/output control macro command.

(JIECK etc.) and identify Aogo slave CPU,
Transfer to B. These slave CPUs 7'L store processing information corresponding to the identification number in the LAM area in each slave CPU. Self 1. J shi, this 2'L is j1? Input/output by refunching to i! , lJ Mamoru 17 is executed.

Figure 1I shows Aij4 separate number (hereinafter referred to as Ordinal)
A conceptual diagram is shown. Ordinal refers to the number of terminals, sensors, actuators, etc. introduced on the hardware side.
and the boat SV g recognized on the software,
This is a number that allows common 63 identification by associating the I/07 address and focus number. Furthermore, the flag (which is only formed on software other than the I10 board) is also an idea that has been extended to all control points of the processor. As shown in Figure 1, connect the Ordinal to slave CPU2/, 2.2.2j's memo IJ It
1 (assigned above. In other words, on RAM (1)
Hyde 4'i ij L BY1? Determine the E No ) and focus number ([3IT No) as shown in Figure 1. In this embodiment, an input port (Di), an output port (
Do) 16 and 7 lugs, 7'L, 3 + bar (t (
32 points).

Figure S shows the input/output one-time control macro that controls our Ordinal Run. SP V-SP CPU 2/~2? The macro parameters in Figure J are the first. Second.・・・・・・
I am so angry. When each task issues these input/output control macros, the monitor decodes the macro commands and executes them (in the expression). The information is transferred to the slave CPUs 2/~n, which control the ordinal on 1tAM.The information is transferred to the master CPU //
This is done by interrupting slave CPU 2/~katana, but what about slave CPU 2/~n? By transferring the information on the RAM to Wr at the 10-gram level other than the 10-gram level including ``J1'' (Di, D.

only) I/O control side 1 is being performed. In Figure 5, @TsE
T is a macro instruction that turns on the ordinal for a specified time, and each task does not need to wait until the ordinal is turned off after issuing this macro instruction. @THE□
In response to the command from P, the slave CPU &1 turns on the ordinal, counts the time by the timer interrupt of Tl (FIG. 1), and turns off the ordinal after the specified time. L th''), each screen is the master CPU
Since it is executed with //, it is necessary to count the time.
It is possible to set multiple timers. By using the above input/output macro instructions, each task realizes unified input/output control regardless of the I10 vote flag.

[Brief explanation of the drawing]

Fig. 1 is a pronk diagram showing a 10-sensor configuration for realizing a sequence control device according to the present invention, Fig. 2 is a state transition diagram of a J task, and Fig. 3 is a diagram explaining formant H and functions of an execution control macro. Figure 5 is a diagram for explaining input/output control macro commands. /l --- Master CPU. ~B ...Soonbu CPU.St...Interval timer.f3...To clock interrupt signal 61...Programmable interrupt controller, 63...Interrupt control, 6S...Drum clock pulse Interrupt signal. Patent applicant Canon Corporation

Claims (1)

[Claims] a master CPU; a slave CPU having a writable storage; means for storing control information in the storage of the slave CPU; A sequence control device characterized in that it is configured to include means for making changes possible after holding the sequence for a certain period of time.