JPS5979353A - Address stop controlling circuit - Google Patents

Abstract

PURPOSE:To lighten the burden of a programmer and effectively perform program debug, by making an arrangement that address stop can be set even when a memory is in operation and a program can be continued properly when the operation is started again. CONSTITUTION:It is assumed that each of FFs 26 and 27 is set. A gate 24 is actuated and turned on and an operation clock from a clock generating circuit 25 is supplied to an address counter/register 21. Then the value of the address counter/register 21 is updated and the coincidence with a value set in a comparison register 22 is detected by a comparator 23 and the FF26 is set. Therefore, another gate is actuated and, as a result, the gate 24 is inactivated and closed and the clock supply is stopped, resulting in the stoppage of the operation. The operation can be restarted and continued properly when the FF26 is reset and the operation clock is supplied to the address counter/register 21 because the coincidence conditions is not realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a control circuit for address stop used particularly during program debugging.

[Technical background of the invention and its problems]

In hardware/software development, a program is executed until it reaches a predetermined address or a predetermined state.
Temporarily suspending operation at that point and checking the status of registers, flags, etc. is a method that has been widely used as an effective means for debugging, etc. For example, by executing a program at a predetermined address, For stopping (address stop), the hardware shown in FIG. 1 is used. That is, address counter/register 1
The comparator 13 compares the value set in the comparison value register 12 with the value set in the comparison value register 12, and if a match is detected, the gate G14
is closed, and therefore the clock generated by the C clock generation circuit 15 is no longer supplied to the address counter, register 11. This interrupts the operation, and is used more frequently than before as a simple and effective means. This is something that has come.

Incidentally, in recent years, processing has become increasingly distributed within processing devices, and for example, when a memory section receives an operation start signal from a calculation control section (CPU), it starts operating, performs reading of data, etc., and performs necessary operations. When the data transfer preparation is completed, the CP
It notifies U of this fact and also transfers the data. Therefore, the CP TJ can perform other processing while the memory section is operating, and can perform efficient operations by taking in and using data from the memory section at a controlled timing.

However, in such a system, if the above-mentioned address stop function is to be realized, the clock supply to the register J1-\ of the address counter 7 will be immediately stopped when an address match occurs. Therefore, clock supply is started without missing data from the memory section,
When the operation was restarted, it was often impossible to continue the operation properly even after 11 and data acquisition.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks. In the above-mentioned processing device, by adding a small amount of σ)-Fware, the CP can be reduced by address stop during memory operation.
(JfilIlfFF"it: memory data C when operation is resumed even if stopped) An object of the present invention is to provide an address/stop control circuit that can correctly execute a program, including taking in the program.

[Summary of the invention]

The present invention is designed to decentralize the processing as described above, and the CP
An address control circuit built into a processing device that operates individually in each device module 753 by a trigger of U, and this control circuit memorizes that the execution address of the program matches the address set from the outside. 1st
&-) A flip-flop with 70 flip-flops and a second flip-flop that indicates that the memory is currently in operation are provided, and a first flip-flop that prohibits the output of the first flip-flop when the output of the second flip-flop is displayed. By providing a gate and a second gate that controls the supply/inhibition of the operation clock to the program counter/register using the first gate output, it is possible to set an address stop even during memory operation, and the operation can be stopped. This eliminates all of the conventional problems that occur when restarting. This reduces the load on the programmer and allows efficient program debugging.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using FIG. 2 and subsequent figures.

FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, 21 is an address counter/register in which the address at which the program should be executed is set, and o22 is a comparison value register in which a comparison value supplied from an external (console channel, maintenance panel, etc.) is set. .

Above address counter/register 21 output and register 2
2 output is fed to a comparator 23. The output of the comparator 23 is fed to a flip-flop 26 where a match is indicated. 027t A flip-flop indicating that the memory is in operation (BUsY) It is. The output of the flip-flop 26 and the inverted output of the flip-flop 27σ are supplied to the Nant gate G2.8. 251 is an operation clock generation circuit. The operating clock generated here is sent to the AND gate G24 together with the output of the Nant gate 28, and is supplied to the address counter/register 2 and other logic. FIG. 3 shows another embodiment of the present invention. FIG. 2 is a block diagram illustrating an example.

In the figure, 31 to 38 are the same numbers as 21 to 28 of the embodiment shown in FIG. The difference from the embodiment shown in FIG. 2 is that the OR gate G39 performs the addition and I/. Comparator 3 for or gate 39
3 outputs and the output of a Noritsubu flop 36 are supplied, and the output subjected to the sum condition is supplied to one input terminal of the Nant gate 38.The operation of the embodiment of the present invention will be described in detail below. do.

First, the operation of the embodiment shown in FIG. 2 will be explained. By some means in advance, the address counter/register 21
It is assumed that values have been set in the and comparison value register 22, and that the flip-flops 26 and 27 have been reset.

Now, an operating clock is generated by the clock generation circuit 25, and this operating clock is applied to the address counter/register 21 via the gate 24.

By the way, the condition for gate 24 is satisfied because the flip-flops 26 and 27 are reset, and (because the condition for gate 28 is not satisfied, as a result, gate 24
is established), and an operating clock is supplied to the address counter/register 2.

As a result, the value of the address counter/register 2 is updated, and when the comparator 23 detects a match with the value set in the comparison value register 22, the flip-flop 26 is set.

By setting the flip-flop 26, the condition of the gate 28 is satisfied, and as a result, the condition of the gate 24 is not satisfied, the gate 24 is closed, and the clock supply is stopped. Therefore, the operation is stopped. When restarting the operation, the operation clock is supplied to the address counter/register 2I by resetting the flip-flop 26, and since the matching condition no longer holds true, the operation can continue. When an operation request is issued to the memory section, the Noritsubu flop 27 is set to 0. At this point, if the comparator 23 detects a match, the flip-flop 26 is set, but the flip-flop 27 is not set. Therefore, the condition of gate 28 does not hold.As a result, the condition of gate 24 remains satisfied, so the clock continues to be supplied to address counter/register 21, and the operation does not stop.

By the way, even if there is no match output from the comparator 23, the flip-flop 26 is not reset, and the fact that there is a match is stored. When the memory operation is completed and the flip-flop 27 is reset, the condition at the gate 28 is satisfied, and as a result, the gate 24 is not established, and the operation is stopped at this point. When starting the operation again, by resetting the flip-flop 26, the memory data will be processed correctly and the operation can be continued normally.
7. Above, we have described the Aritz flop 26 as a set/reset type flip-flop, but for example, if it is a clock type flip-flop such as a D type Noritsub flop, it can be used as an OR gate 395 as shown in Figure 3. In addition, the same function can be realized. That is, due to the existence of this OR gate 39, the delay until the flip-flop 36 changes to the clock can be eliminated.

〔Effect of the invention〕

As described above, according to the present invention, since the address stop can be set and the program can be continued correctly even during memory operation, it is effective in program development, particularly in the troublesome stages of microprogram development. That is, Deno (
Since the address stop can be set without worrying about whether or not there is a memory access at the time of writing, the load on the programmer is reduced and efficient denomination can be performed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the configuration of a conventional address stop control circuit σ), Fig. 2 is a block diagram showing an embodiment of the present invention and Fig. 3 is a block diagram showing all embodiments of the present invention. 0 21.31...address counter/register, 22.
32... Comparison value register, 23.33... Comparator,
24.34...AND gate, 25,35゛'°clock generation circuit, 26.36, 27.37...flip-flop, 28.38...Nand gate, 39...
Orgate. Figure 2? 133 Figure 260

Claims (1)

[Claims] Comparison that compares the address counter, where the program execution address is successively updated and set based on the clock generated by the clock generation circuit, and the value of the register where the comparison value is set, and detects an address match condition. a first flip-flop 70 for storing a coincidence signal which is the output of the comparator, and a second 7-lip 70 for storing that the memory is in operation; an address comprising: a first gate that inhibits the output of the first flip-flop; and a second gate that uses the first gate output to control clock supply to the address counter.・Stop control circuit 0