JPS62120551A - information processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] An information processing device is provided with an external means for stopping an instruction when a match is made with a required address, the instruction stopping means is provided with a storage circuit for storing a match detection state, and a waiting state is provided. Eliminates state-related delays and improves cycle time.

[Industrial application field]

The present invention relates to an information processing device, and particularly to a required address.
The present invention relates to an information processing device externally equipped with means for stopping commands.

Information processing devices are widely used in the fields of information processing and communications. Information processing devices are generally operated by microprograms stored in control storage. A large-scale integrated circuit (hereinafter referred to as LSI) is attached in order to upgrade the functionality of the existing information processing device or to investigate a failure in the information processing device.

Signals transferred between this attached LSI and the LSI stored in the information processing device itself and in charge of processing operations have a slower transfer speed than LSI internal signals. Therefore, in order to operate the attached LSI normally, the cycle time must be reduced, and there is a demand for an information processing device that does not require this cycle time reduction.

[Conventional technology]

An information processing apparatus that is externally equipped with a stopping means for stopping a microprogram when a required address is reached in order to investigate a fault has conventionally been constructed as shown in FIG. That is, the information processing device system is composed of a control storage (CS) 3 that stores a microprogram and an LSI-1 that operates as an information processing device.

Furthermore, LS L 1 includes a sequence control unit 1-1 that controls the microprograms to be executed gradually, a register 1-2 that stores the address of the microprogram to be executed (hereinafter referred to as a microinstruction), and a register 1-2 that stores the next address for execution. It consists of registers (MIR) 1-3. The sequence control unit 1-1 outputs a microinstruction stop signal (I(LTST)) and an execution wait signal (-AIT) of the LSI-1, as well as other control signals for controlling other parts.

Set enable circuit 1-4 controls register 1-2. For example, when HLTST, -^IT, and other stop signals are input to the set enable circuit 1-4, register 1
-2 address up is stopped.

L acts as an instruction stopping means to stop microinstructions.
SI-2 includes register 2-1 that stores a stop instruction address that instructs to stop, register 2-2 that sets the address (MIA2) of a microinstruction instructed by LSI-1, and registers 2-1 and 2-2. It consists of a coincidence detection circuit 2-3 for detecting coincidence of the contents of the register 2-2 and a cent enable circuit 2-4 for the register 2-2.

For example, when the -AIT signal is output from the sequence control unit 1-1, it is delayed by α and becomes the -AIT2 signal, and the microinstruction update (MIA2) of the register 2-2 is stopped via the set enable circuit 2-4. do.

The microinstructions are executed gradually, but if access is put on hold for some reason such as a memory request (for example, due to a request conflict on the shared memory bus), the sequence control unit 1-1 stops updating the microinstructions. - Outputs AIT signals - AITI and WAIT2.

The above state is as shown in FIG. That is, when a waiting state occurs for some reason during the execution of a microinstruction, the sequence control section outputs the -AIT signal. With this signal, WAITI becomes valid at point a after a slight delay in LSI-1, and the update of MIAI is suppressed at point b and point C.

On the other hand, the WAIT2 signal that stops MIA2 is delayed by α and the delay within the LSI-2, and WAIT2 becomes valid at point C. Therefore, I'll^2 is b
It will be updated at point 4, and the update will be inhibited in E state at point 4. FIG. 5 shows the operation of the address stop circuit of FIG. 3 in this state.

In other words, if you want to stop at address D, WAIT2
In the old ^2, D is completed in one microinstruction execution cycle, and updates are inhibited in the state of E, so
The coincidence detection circuit is an HLTST (
This causes the inconvenience that the line (dotted line in the figure) is not valid.

To deal with this, the clock must be slowed down (or locked to include at least point C shown in FIG. 4), and the processing speed of the processing device must be slowed down.

[Problem that the invention seeks to solve]

As mentioned above, in conventional information processing devices, due to the delay in the waiting state generation signal, the cycle must be delayed to ensure that the coincidence detection signal is received by the sequence control unit, making it difficult to increase the cycle and the system It was difficult to improve the performance of

The present invention was created in view of these points, and an object of the present invention is to provide an information processing device that has a simple configuration and can be cycled up without being affected by cycles due to waiting states.

[Means for solving problems]

The instruction stopping means of the information processing device is configured to include a storage circuit for storing the coincidence detection state.

[Effect]

When the microinstruction reaches the required address, the coincidence detection means outputs an output signal, this output signal is stored in the memory circuit, and when the execution of the microinstruction at the address is completed, the microinstruction is stopped and placed in a waiting state. It is possible to stop microinstructions that are not affected by this.

[Embodiment] Fig. 1 is a circuit diagram of an embodiment of the present invention, and the difference from the conventional one is that a flip-flop circuit (hereinafter referred to as FF circuit) 3 which operates as a storage means is provided in the -number output circuit 2-3. and the OR circuit 3-1, and the MIA2 of the register 2-2.
The point is that the WAIT signal, which is a signal that prohibits the change of the data, is not used.

The fact that a match has been detected is stored in the FF circuit 3, and the FF circuit 3-
1, and directly input the -number output to the output circuit 3-1.
Enter. Note that the coincidence signal of the FF circuit is taken out when a wait (WAIT) signal is output.

A feature of the present invention is that a signal either directly from the -number output circuit 2-3 or once received by the FF circuit 3 is input to the sequence control section 1-3.

The operation will be explained with reference to FIG. Stop address D
is set in the register 2-1, the address of the microinstruction, that is, the contents of the register 2-2 becomes D, and when the -number output circuit 2-3 detects a match of the addresses, the FF circuit 3 stores the match detection. .

This stored coincidence detection state informs the sequence control unit 1-1 that there is a coincidence from three points onwards while the -^IT signal is being output. The sequence control unit 1-1
A TST signal will be output.

〔Effect of the invention〕

As described above, according to the present invention, the cycle-up failure can be removed with an extremely simple circuit configuration, which is extremely effective in improving device performance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart of the present invention, FIG. 3 is a configuration diagram of main parts of a conventional information processing device, FIG. 4 is a time chart of a conventional method, and FIG. The figure is a time chart when the waiting signal of the conventional system is eliminated. In the figure, 1 is an information processing device, 1-1 is a sequence control section, 2 is an instruction stop means, 2-3 is a coincidence detection circuit, and 3 is a storage circuit.

Claims (1)

[Claims] An information processing device (1) that sequentially executes instructions, and an instruction stopping means (1) that stops the instructions when the instructions match a required address.
2), wherein the instruction stopping means (2) is provided with a storage circuit (3) for storing a match detection state.