JPS5882569A - Field effect transistor - Google Patents

Abstract

PURPOSE:To enhance greatly voltage withstand performance between a drain and a source by a method wherein the poly-Si layer for a gate electrode is laminated on a gate oxide layer interposing an alumina layer between them. CONSTITUTION:The N<+> type source layer 5 is doubly diffused in the P type base layer 4 in an N type Si substrate 1, the poly-Si electrode 3' is provided on the gate oxide layer 2' interposing the alumina layer 6 between them, the oxide layer 2' is accumulated again, openings are formed selectively, and the electrodes S, G are adhered to the source layer 5, the gate electrode 3'. By this constitution, because the alumina layer blocks diffusing impurities, reduction of the withstand voltage according to penetration of impurities to the substrate from the poly-Si layer 3' is not generated when the source is diffused. The alumina layer is effective even when it is provided at the part other than the gate electrode part, density of the surface state is reduced, mobility of two times or more can be obtained, and an influence of Na ions in the SiO2 film is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION l) Technical Field of the Invention The present invention relates to field effect transistors, and in particular to improvements in the gate structure of silicon gate field effect transistors.

2) *Future technology: 4S, which uses the Kamekai Yomai transistor as a power device
A double diffusion type moss structure was built. As shown in Figure 41, a gate oxide layer (2J is formed on an N-type substrate or drain region (11), and a polycrystalline silicon layer (J is used as a mask to form a base region (4) and source region (5) are formed by double diffusion.In order to use the above structure as a power device, the channel length formed by double diffusion is generally 3μ or less, W/L (WF
The i-channel @) is enlarged to achieve a large current.

3) Conventional Problems The above-mentioned W requires billions or more, and it is very difficult to make it uniformly less than 3μ over this entire area, which lowers the yield.

4) Purpose of the invention ζO departure @ is intended to improve the conventional problems.

5) Configuration (I! approx.) The polycrystalline silicon layer of the gate electrode is
-) It is characterized by being constructed by laminating on an oxide layer.

6) Example (Structure, function and effect) As shown in FIG.
f (3') are laminated with an alumina layer (6) interposed therebetween. An example of the structure of the gate electrode part is that the thickness of the gate oxide layer (layer between the top surface of the substrate and the alumina layer) is 500 mm.
X, the thickness of the alumina layer is soooo! , the thickness of the polycrystalline silicon layer is 500X. Also, the base area (4)
The polycrystalline silicon layer (3) was used as a mask to form the source region (5), and boron was ion-implanted into the base region (4) of P conductivity type, and P into the NO source region (5).
Double diffusion is formed by sequentially diffusing phosphorus using OC4. Furthermore, a silicon oxide layer is applied to the source region (
5) A hole is made to expose a part of each of the gate electrode (3'), a metal layer is deposited to lead these out, and butter kneading is performed to form a source electrode (S) and a gate electrode (G). A lead-out electrode group is formed together with the drain electrode (2) provided on the opposite main surface of the substrate. With this structure, improvements in the electrical characteristics of the MOS transistor, which will be described later, were achieved. Note that the Al i layer is not limited to the gate electrode part.
There is a blocking effect by providing a MOS O differentiated oxidation layer.

7) Effects of the invention (a) It is possible to reduce the interface ratio position.
The interface mobility can be more than twice as large as the conventional 400aL'Vs, and the same current can be obtained even if L is changed from 3s to 6μ, for example, there are fewer difficulties in device fabrication, and the yield is lower. improves. First, it is possible to improve the characteristics of conventional OLs, and it is also possible to reduce the size of the chip.

(b) Aluina layer line The negative charge on the interface between Alina and silicon oxide reduces the influence of sodium ions in the silicon oxide, making it easier to manufacture N-channel enhancement devices.

(c) Conventionally, during base diffusion and source diffusion, impurities diffused into the polycrystalline silicon layer and left the gate deterioration layer in the center, forming an undesired diffusion layer in the substrate (drain region) and lowering the drain-source breakdown voltage. However, it has a large plotter effect against impurities diffused into the alumina layer, dramatically improving breakdown voltage performance and improving yield.

(d) Radiation withstand voltage also increases.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional field effect transistor, and FIG. 2 is a sectional view of a field effect transistor according to an embodiment. l Drain region (substrate) 2.2゛ Gate oxide layer 3.3' Polycrystalline silicon layer (gate electrode) 4
Base area 5 Source area 6 Albas layer agent Patent attorney Inoue - Male 1st diagram 2nd diagram

Claims (1)

[Claims] In a silicon gate field effect transistor in which the base region and the source region are formed of double diffusion layers, the polycrystalline silicon layer of the gate electrode is formed by laminating the polycrystalline silicon layer with an alumina layer interposed therebetween. silicon gate field effect transistor.